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GS1503 HD EMBEDDED AUDIO CODEC
DATA SHEET FEATURES * complies with SMPTE 292M and SMPTE 299M * single chip HD embedded audio solution * operates as an embedded audio multiplexer or demultiplexer * full support for 48kHz synchronous 24-bit audio * support for 8 channels of audio per device * cascadable architecture supports up to 16 audio channels * integrated scrambler/descrambler and word alignment * CRC error detection and insertion * audio control packet insertion and extraction * arbitrary data packet insertion and extraction * 3.3V power supply with 5V tolerant I/O * 144 pin LQFP package APPLICATIONS HD SDI Embedded Audio ORDERING INFORMATION
PART NUMBER GS1503-CFZ PACKAGE 144 pin LQFP TEMPERATURE 0C to 70C
DESCRIPTION The GS1503 is a highly integrated, single chip solution for embedding/extracting digital audio streams into and out of high definition digital video signals. The GS1503 supports insertion/extraction of 24-bit synchronous audio data with a 48kHz sample rate. Audio signals with different sample rates may be converted to 48kHz by using audio sample rate converters before or after the GS1503. Each GS1503 supports all processing required for embedding/extracting up to eight digital audio channels in the horizontal ancillary data space of the video chroma channel. Two GS1503's can be cascaded for insertion/ extraction of up to 16 audio channels with no external glue logic. The GS1503 supports embedding/extracting of audio control and arbitrary data packets in the horizontal ancillary data space of the video luma channel. It also supports line CRC detection and insertion. The GS1503 supports HD video standards at 74.25MHz and 74.25/1.001MHz rates. It has an on chip SMPTE compliant scrambler/de-scrambler, and integrated word alignment. Use the GS1503 with Gennum's GS1545 or GS1522 for two chip HD SDI receive or transmit solutions. The GS1503 operates from a single 3.3V power supply with 5V tolerant I/O and is packaged in a 144 pin LQFP package.
GS1503
DSCBYPASS
EXTH
EXTF
SCRBYPASS
VIN[19:0]
20
De-scrambler & Word Alignment
20 20 TRS Inserter 20 CRC Inserter & Scrambler 20 VOUT[19:0] VIDEO_DET OPERATE ERROR CRC_ERR
VM[3:0]
4
Video Detection & Synchronization ANCI Timing Generation
4
CPUADR[8:0] CPUDAT[7:0] CPUCS, CPUWE, CPURE PKT[7:0] PKTEN AIN1/2 AIN3/4 AIN5/6 AIN7/8 WCINA/B
9 8 3 Host Interface
Control Packet Mux
HOST INTERFACE
8
Arbitrary Packet Mux
PKTENO HOST INTERFACE
4 Audio Input Interface 2 AM[1:0] MUTE Audio Packet Mux
2
MULTIPLEX MODE BLOCK DIAGRAM
Revision Date: May 2005 GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com www.gennum.com
Document No. 15879 - 4
DSCBYPASS
ANCI
SCRBYPASS
VIN[19:0]
20
De-scrambler & Word Alignment Video Detection & Synchronization ANCI Timing Generation
20
Delete ANCI
20
CRC Inserter & Scrambler
20
VOUT[19:0] VIDEO_DET OPERATE ERROR CRC_ERR PKT[7:0] PKTEN
VM[3:0]
4
4
Arbitrary Packet Demux
8 HOST INTERFACE
GS1503
Control Packet Demux 9 8 3 Host Interface Audio Packet Demux
HOST INTERFACE AOUT1/2 AOUT3/4 AOUT5/6 AOUT7/8 WCOUTA/B
CPUADR[8:0] CPUDAT[7:0] CPUCS, CPUWE, CPURE
4 Audio Output Interface 2 AM[1:0] MUTE
2
DEMULTIPLEX MODE BLOCK DIAGRAM
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage Input Voltage (any input) Operating Temperature Storage temperature Lead Temperature (soldering, 10 sec.) VALUE -0.3V to 4.0V -0.3 to 5.5V 0C to 70C -65C to 150C 230C
DC ELECTRICAL CHARACTERISTICS
TA = 0C to 70C unless otherwise shown.
PARAMETER Supply Voltage Supply Current Input Current Hi-Z Output Leakage Current Output Voltage, Logic High Output Voltage, Logic Low Input Voltage, Logic High Input Voltage, Logic Low Input Capacitance Output Capacitance I/O Capacitance
SYMBOL VDD IDD IIN IOZ VOH VOL VIH VIL CI CO CIO
CONDITIONS 3.3V operating range VDD = 3.3V
MIN 3.0
TYP 3.3 270
MAX 3.6
UNITS V mA
-1 -1 IOH = -12mA IOL = 12mA TTL Level TTL Level f = 1MHz, VDD = 0V f = 1MHz, VDD = 0V f = 1MHz, VDD = 0V VDD-0.4 2.0 -
-
1 1 0.4 0.8 10 10 10
A A V V V V pF pF pF
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AC ELECTRICAL CHARACTERISTICS
VDD = 3.3V 5%, TA = 0C to 70C unless otherwise shown.
PARAMETER Video Clock Frequency Video Clock Pulse Width Low Video Clock Pulse Width High Video Input Data Setup Time Video Input Data Hold Time Video Output Data Delay Time Video Output Data Hold Time Audio Clock Frequency Audio Clock Pulse Width Low Audio Clock Pulse Width High Audio Input Data Setup Time Audio Input Data Hold Time Audio Output Data Delay Time Audio Output Data Hold Time Reset Pulse Width Device Latency
SYMBOL
CONDITIONS
MIN -
TYP 74.25 6.144 53 53
MAX 80 8.5 20.0 53 53
UNITS MHz ns ns ns ns ns ns MHz ns ns ns ns ns ns ms PCLKs
tVPWL tVPWH tVS tVH tVOD tVOH With 10pF loading With 10pF loading
5.0 5.0 3.5 1.0 1.0 -
GS1503
tAPWL tAPWH tAS tAH tAOD tAOH tRESET Multiplexer Mode Demultiplexer Mode With 10pF loading With 10pF loading
60 60 10.5 1.0 1.0 1 53 53
t VS VCLK
t VH
Data*
* VIN[19:0],
EXTF, EXTH, PKTEN, PKT[7:0]
Fig. 1 Video Data Input Setup & Hold Time
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t VOH
t VOD
VCLK
GS1503
Data*
* VOUT[19:0], EXTF, EXTH, PKTEN, PKT[7:0]
Fig. 2 Video Data Output Delay & Hold Time
t AS ACLKA/B
t AH
Data*
* WCINA, AIN1/2, AIN3/4, WCINB, AIN5/6, AIN7/8
Fig. 3 Audio Data Input Setup & Hold Time
t AOH
t AOD
ACLKA/B
Data*
* AOUT1/2, AOUT3/4, AOUT5/6, AOUT7/8
Fig. 4 Audio Data Output Delay & Hold Time
VDD(min) VDD t RESET RESET t RESET
Fig. 5 Reset Timing
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HOST INTERFACE Mode A (CPU_SEL set HIGH)
PARAMETER Read Cycle Time Read Chip Select Setup Time Read Address Setup Time Read Data Output Delay Time Read Data Hold Time Write Cycle Time Write Chip Select Setup Time Write Address Setup Time Write Data Setup Time Write Data Hold Time NUMBER 1 2 3 4 5 6 7 8 9 10 MIN 50 0 15 0 50 10 10 10 0 TYP MAX 15 UNITS ns ns
GS1503
ns ns ns ns ns ns ns ns
Read Cycle 1 CPUADR[8:0] 2 CPUCS Address 7
Write Cycle 6 Address
CPURE 3 CPUWE 8
CPUDAT[7:0] 4
Valid Data 5
Valid Data 9 10
Fig. 6 Host Interface Mode A Timing (CPU_SEL set HIGH)
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Mode B Read Cycle (CPU_SEL set LOW)
PARAMETER Read Address Cycle Time Read Cycle Time Read Enable Setup Time Read Address Setup Time Read Chip Select Setup Time Read Chip Select Hold Time Read Data Output Delay Time Read Data Hold Time NUMBER 1 2 3 4 5 6 7 8 MIN 80 80 20 20 10 0 0 TYP MAX 10 UNITS ns ns
GS1503
ns ns ns ns ns ns
1 CPUADR[1:0] 01
1 00
2 11 8
CPUDAT[7:0]
Upper Address
Lower Address 7
Read Data
CPUCS
CPUWE 5 4 3 6 5 4 3 6 3 5 6
Fig. 7 Host Interface Mode B Read Cycle Timing (CPU_SEL set LOW)
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Mode B Write Cycle (CPU_SEL set LOW)
PARAMETER Write Address Cycle Time Write Cycle Time Write Enable Setup Time Write Address Setup Time Write Chip Select Setup Time Write Chip Select Hold Time Write Data Setup Time Write Data Hold Time NUMBER 1 2 3 4 5 6 7 8 MIN 80 80 20 20 10 0 30 0 TYP MAX UNITS ns ns ns
GS1503
ns ns ns ns ns
1 CPUADR[1:0] 01
1 00
2 10 8
CPUDAT[7:0]
Upper Address
Lower Address
Write Data 7
CPUCS
CPUWE 5 4 3 6 5 4 3 6 3 5 6
Fig. 8 Host Interface Mode B Write Cycle Timing (CPU_SEL set LOW)
Table 1: Host Interface Mode B Control Codes
CPUADR[1:0] 01 00 11 10 Data Bus Operation Upper Address Lower Address Read Data Write Data
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PIN CONNECTIONS
GND CPUWE CPURE CPUCS VDD CPUDAT7 CPUDAT6 CPUDAT5 CPUDAT4 CPUDAT3 CPUDAT2 VDD CPUDAT1 CPUDAT0 CPUADR4 CPUADR3 CPUADR2 CPUADR1 CPUADR0 CPUADR5 GND VCLK GND DEC_MODE VDD CPUADR6 CPUADR7 CPUADR8 GND AOUT7/8 AOUT5/6 AOUT3/4 AOUT1/2 WCOUTB WCOUTA VDD
GS1503
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
VDD VIN19 VIN18 VIN17 GND VIN16 VIN15 VIN14 VDD VIN13 VIN12 VIN11 GND VIN10 VIN9 VIN8 VDD VIN7 VIN6 VIN5 GND VIN4 VIN3 VIN2 VDD VIN1 VIN0 CPU_SEL AM1 AM0 VM3 VM2 VM1 VM0 RESET GND
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
GS1503 TOP VIEW
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
GND VOUT19 VOUT18 VOUT17 VDD VOUT16 VOUT15 VOUT14 GND VOUT13 VOUT12 VOUT11 VDD VOUT10 VOUT9 VOUT8 GND VOUT7 VOUT6 VOUT5 VDD VOUT4 VOUT3 VOUT2 GND VOUT1 VOUT0 VIDEO_DET EXTF EXTH RSV RSV RSV RSV SCRBYPASS VDD
VDD AIN7/8 AIN5/6 AIN3/4 AIN1/2 WCINB WCINA DSCBYPASS PLLCNTB PLLCNTA CASCADE MUTE ANCI VDD MUX/DEMUX GND ACLKA GND ACLKB GND ERROR OPERATE CRC_ERROR PKTENO PKTEN PKT7 VDD PKT6 PKT5 PKT4 VDD PKT3 PKT2 PKT1 PKT0 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
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PIN DESCRIPTIONS
NUMBER 1, 14, 27, 31, 37, 52, 60, 68, 73, 84, 97, 104, 109, 117, 125, 133 2 SYMBOL VDD TYPE +3.3V power supply pins. DESCRIPTION
GS1503
AIN7/8
I
Audio signal input for channels 7 and 8. AES/EBU digital audio data is bi-phase mark encoded. For all non-AES/EBU input modes, bi-phase mark encoding is not required. Audio signal input for channels 5 and 6. AES/EBU digital audio data is bi-phase mark encoded. For all non-AES/EBU input modes, bi-phase mark encoding is not required. Audio signal input for channels 3 and 4. AES/EBU digital audio data is bi-phase mark encoded. For all non-AES/EBU input modes, bi-phase mark encoding is not required. Audio signal input for channels 1 and 2. AES/EBU digital audio data is bi-phase mark encoded. For all non-AES/EBU input modes, bi-phase mark encoding is not required. 48kHz word clock for channels 5 to 8. Used only when operating in Multiplex Mode and when the audio source is not an AES/EBU data stream. This pin should be grounded when inputting AES/EBU digital audio data or when operating in Demultiplex Mode (DEC_MODE set LOW). 48kHz word clock for channels 1 to 4. Used only when operating in Multiplex Mode and when the audio source is not an AES/EBU data stream. This pin should be grounded when inputting AES/EBU digital audio data or when operating in Demultiplex Mode (DEC_MODE set LOW). Descrambler bypass. When set LOW, the internal SMPTE 292M descrambler is enabled. When set HIGH, the internal SMPTE 292M descrambler is bypassed. The video input to the device must be word aligned. Audio clock PLL control signal for channels 5 to 8. Audio clock PLL control signal for channels 1 to 4. Cascade mode select. When set HIGH, the GS1503 will default to audio groups 3 and 4. Two GS1503 devices can then be cascaded in series to allow up to 16 channels of audio to be multiplexed or demultiplexed (only one device requires CASCADE to be set HIGH). When set LOW, the GS1503 will default to audio groups 1 and 2. Audio mute. In Multiplex Mode, when set HIGH, the embedded audio packets are forced to '0'. In Demultiplex Mode, when set HIGH, the audio output data is forced to "0". Ancillary data delete select. Valid in Demultiplex Mode only. When set HIGH, all ancillary data packets are removed from both the Luma and Chroma channels of the input video signal. The data contained in the packets are output at the corresponding pins. When set LOW, all ancillary data packets remain in the video signal. See Section 2-11. Mode of operation. When set LOW, the GS1503 operates in Multiplex Mode. When set HIGH, the GS1503 operates in Demultiplex Mode.
3
AIN5/6
I
4
AIN3/4
I
5
AIN1/2
I
6
WCINB
I
7
WCINA
I
8
DSCBYPASS
I
9 10 11
PLLCNTB PLLCNTA CASCADE
O O I
12
MUTE
I
13
ANCI
I
15
MUX/DEMUX
I
16, 18, 20, 36, 48, 56, 64, 72, 80, 86, 88, 108, 113, 121, 129, 144 17 19 21
GND
-
Device ground.
ACLKA ACLKB ERROR
I I O
Input audio signal clock at 6.144 MHz (128 fs) for channels 1 to 4. Input audio signal clock at 6.144 MHz (128 fs) for channels 5 to 8. Format error indicator. When HIGH, the incoming video data stream contains TRS errors or there are errors within the incoming ancillary data packets.
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PIN DESCRIPTIONS (Continued)
NUMBER 22 SYMBOL OPERATE TYPE O DESCRIPTION Audio processing indicator. When HIGH, audio data is being multiplexed or demultiplexed. CRC error indicator. Will be set HIGH when a CRC error is detected in the incoming video data stream.
23
CRC_ERROR
O
GS1503
24
PKTENO
O
Arbitrary data packet timing signal. Valid in Multiplex Mode only. Will be HIGH when arbitrary data packets can be input to the device. This signal is only valid when multiplexing arbitrary data packets via the PKT[7:0] bus. See Figure 30 for timing. Arbitrary data packet enable. In Multiplex Mode, PKTEN is an input and must be set HIGH two VCLK cycles after the PKTENO signal goes HIGH. Arbitrary packet data is input to the device two VCLK cycles after PKTEN is set HIGH. In Demultiplex Mode, PKTEN is an output and is set HIGH two VCLK cycles before the device outputs arbitrary packet data. See Figures 30 and 42. Arbitrary data I/O bus. PKT[7] is the MSB and PKT[0] is the LSB. In Multiplex Mode, the user must input the arbitrary data packet words starting from the data identification (DID) to the last user data word (UDW) according to SMPTE 291M. The GS1503 internally converts the data to 10 bits by generating the parity bit (bit 8) and inversion bit (bit 9). The checksum (CS) word is also generated internally. In Demultiplex Mode, the GS9023 outputs the arbitrary data packet words starting from the DID to the last UDW. See Figures 30 and 42. Scrambler bypass. When set LOW, the output video stream is scrambled according to SMPTE 292M and NRZ(I) encoded. When set HIGH, the scrambler and NRZ(I) encoder are bypassed. Connect to ground.
25
PKTEN
I/O
26, 28, 29, 30, 32, 33, 34, 35
PKT[7:0]
I/O
38
SCRBYPASS
I
39, 40, 41, 42 43
RSV
-
EXTH
I/O
Horizontal sync signal. The GS1503 outputs a horizontal sync signal derived from the incoming TRS. In Multiplex Mode, with EXT_SEL set HIGH in the Host Interface, a horizontal sync signal can be input to the device for TRS and line number insertion. Field sync signal. The GS1503 outputs a field sync signal derived from the incoming TRS. In Multiplex Mode, with EXT_SEL set HIGH in the Host Interface, a field sync signal can be input to the device for TRS and line number insertion. For progressive formats, a signal with a high to low transition at the position of line one must be provided. See Figures 14 and 15. Video input signal detection. Indicates that the device has detected a valid video input stream. NOTE: When EXT_SEL is set HIGH in the Host Interface, VIDEO_DET will indicate when valid EXTH and EXTF signals have been detected.
44
EXTF
I/O
45
VIDEO_DET
O
71, 70, 69, 67, 66, 65, 63, 62, 61, 59, 58, 57, 55, 54, 53, 51, 50, 49, 47, 46 74 75 76
VOUT[19:0]
O
Parallel digital video signal output. VOUT[19] is the MSB and VOUT[0] is the LSB.
WCOUTA WCOUTB AOUT1/2
O O O
48kHz word clock for channels 1 to 4. Valid only when operating in Demultiplex Mode. 48kHz word clock for channels 5 to 8. Valid only when operating in Demultiplex Mode. Audio signal output for channels 1 and 2. The AES/EBU digital audio output is bi-phase mark encoded. In both non-AES/EBU modes, the output is not bi-phase mark encoded. Audio signal output for channels 3 and 4. The AES/EBU digital audio output is bi-phase mark encoded. In both non-AES/EBU modes, the output is not bi-phase mark encoded. Audio signal output for channels 5 and 6. The AES/EBU digital audio output is bi-phase mark encoded. In both non-AES/EBU modes, the output is not bi-phase mark encoded.
77
AOUT3/4
O
78
AOUT5/6
O
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PIN DESCRIPTIONS (Continued)
NUMBER 79 SYMBOL AOUT7/8 TYPE O DESCRIPTION Audio signal output for channels 7 and 8. The AES/EBU digital audio output is bi-phase mark encoded. In both non-AES/EBU modes, the output is not bi-phase mark encoded. Demultiplex Mode select. Valid in Demultiplex Mode only. When set HIGH, the GS1503 requires a 48kHz word clock input at WCINA and WCINB. This word clock must be synchronous to the word clock used to embed the audio data. The embedded audio clock phase information in the ancillary data packet will be ignored. See Section 2-11. Video clock signal input. Host Interface address bus. CPUADR[8] is the MSB and CPUADR[0] is the LSB. In Host Interface Mode B (CPU_SEL set LOW), CPUADR[1:0] are used as the Host Interface control bus. See Table 1. Host Interface data bus. CPUDAT[7] is the MSB and CPUDAT[0] is the LSB. In Host Interface Mode B (CPU_SEL set LOW), CPUDAT[7:0] are used as the Host Interface address and data bus.
85
DEC_MODE
I
GS1503
87 81, 82, 83, 89, 94, 93, 92, 91, 90 103, 102, 101, 100, 99, 98, 96, 95 105 106
VCLK CPUADR[8:0]
I I
CPUDAT[7:0]
I/O
CPUCS CPURE
I I
Chip select for Host Interface. Active LOW. Read enable for Host Interface. Active LOW. In Host Interface Mode B (CPU_SEL set LOW), this input is not used. Write enable for Host Interface. Active LOW. In Host Interface Mode B (CPU_SEL set LOW), this input is used as the Host Interface control enable. Parallel digital video signal input. VIN[19] is the MSB and VIN[0] is the LSB.
107
CPUWE
I
110, 111, 112, 114, 115, 116, 118, 119, 120, 122, 123, 124, 126, 127, 128, 130, 131, 132, 134, 135 136
VIN[19:0]
I
CPU_SEL
I
Host Interface mode select. When set HIGH, the GS1503 is configured for Host Interface Mode A. When set LOW, the GS1503 is configured for Host Interface Mode B. Audio format select. In Multiplex Mode, AM[1:0] indicates the input audio data format. In Demultiplex Mode, AM[1:0] indicates the output audio data format. AM[1] is the MSB and AM[0] is the LSB. See Tables 3 and 11. Video standard select. VM[3] is the MSB and VM[0] is the LSB. See Table 2 or 10.
137, 138
AM[1:0]
I
139, 140, 141, 142 143
VM[3:0]
I
RESET
I
Device reset. Active LOW.
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DETAILED DESCRIPTION 1. MULTIPLEX MODE
1.1 FUNCTIONAL OVERVIEW
Up to a maximum of 8 channels of 48kHz digital audio can be multiplexed per device. The audio input format can be selected as either AES/EBU, or one of two serial audio data input modes. A maximum of 16 channels of audio can be multiplexed by serially cascading two devices. Audio control packets, as defined in SMPTE 299M, can also be multiplexed to provide information to receivers about the nature of the embedded audio data. The contents of the audio control packet can be programmed via the Host Interface. The GS1503 will also multiplex arbitrary data packets as defined in SMPTE 291M. The arbitrary data packets can serve as an auxiliary data signal for proprietary applications. The GS1503 can be configured to multiplex arbitrary data packets, input via the Host Interface or using dedicated external pins. Up to a maximum of 255 8-bit words can be multiplexed (excluding Ancillary Data Flags and Checksum). To use the GS1503 in Multiplex Mode, set the MUX/DEMUX external pin LOW.
1.2 VIDEO STANDARD
The GS1503 HD Embedded Audio CODEC fully supports the multiplexing of Audio Data Packets, Audio Control Packets and Arbitrary Data Packets as per SMPTE 291M and 299M. The device can be configured to operate with all video standards defined in SMPTE 292M, levels A through M. The GS1503 also supports the 1080/24PsF, 25PsF and 30PsF video formats as described in SMPTE RP211. The video input format can be one of the following configurations: 10-bit Y and Cb/Cr input with TRS and Line Numbers 8-bit Y and Cb/Cr input with TRS and Line Numbers 10-bit or 8-bit Y and Cb/Cr input without TRS and Line Numbers (GS1503 will insert TRS and Line Numbers based on EXTF and EXTH inputs) 20-bit scrambled input The video output format can be one of the following configurations: 20-bit scrambled output 10-bit Y and Cb/Cr output
GS1503
The video standard is selected from the VM[3:0] external pins or VM[3:0] bits 3-0 in Host Interface register 000h. To configure the video standard via the Host Interface, VM_SEL bit 7 in Host Interface register 000h must be set HIGH. The GS1503 will default to the VM[3:0] external pin setting. The supported video standards are listed in Table 2.
Table 2: Supported Video Standards
VM [3:0] 1110b 1100b 1000b 1010b 1111b 0010b 0100b 0110b 0000b 0001b 0011b 0101b 0111b INPUT FORMAT 1035i (30 & 30/1.001 Hz) 1080i (25 Hz) 1080i/1080sF (30 & 30/1.001 Hz) 1080i/1080sF (25 Hz) 1080sF (24 & 24/1.001 Hz) 1080p (30 & 30/1.001 Hz) 1080p (25 Hz) 1080p (24 & 24/1.001 Hz) 720p (60 & 60/1.001 Hz) 720p (30 & 30/1.001 Hz) 720p (50 Hz) 720p (25 Hz) 720p (24 & 24/1.001 Hz) All other settings are reserved REFERENCE SMPTE DOCUMENT 260M 295M 274M, RP211 274M, RP211 RP211 274M 274M 274M 296M 296M 296M 296M 296M G, H I J, K L, M SMPTE 292M LEVEL A, B C D, E F
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Register Settings
NAME VM_SEL DESCRIPTION 0: External pin select 1: Register select VM[3:0] Video formal selection (VM[3] is MSB) 3-0 See Table 2 0 ADDRESS 000 BIT 7 SETTING 1 DEFAULT 0
GS1503
1.3 VIDEO INPUT FORMAT 1.3.1 10-bit Y and Cb/Cr Input Video with TRS and Line Numbers
GS1503 Y[9:0] VIN[19:10]
Cb / Cr [9:0]
VIN[9:0]
EXTF +3.3V EXTH
DSCBYPASS
Fig. 9 Configuration for 10-bit Y and Cb/Cr Input Video with TRS and Line Numbers
0
3
CRC0
CRC1
10-bit
LN0
XYZ
LN1
8
XYZ
000
3FF
000
3FF
000
000
V0
Y, C b/Cr
Video
EAV
SAV
Fig. 10 Video Input Format 10-bit with TRS and Line Numbers
Register Settings
NAME EXT_SEL DESCRIPTION 0: EXTH/EXTF output select 1: EXTH/EXTF input select 8BIT_SEL 0: 10-bit mode select 1: 8-bit mode select DSCBYPASS 0: Descrambling enabled 1: Bypass descrambling 0 1 0 1 0 0 ADDRESS 001 BIT 3 SETTING 0 DEFAULT 0
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Vn
1.3.2 8-bit Y and Cb/Cr Input Video with TRS and Line Numbers
GS1503 Y[9:0] VIN[19:12]
VIN[11:10]
GS1503
C b/ C r[9:0]
VIN[9:2] EXTF VIN[1:0]
+3.3V EXTH
DSCBYPASS
Fig. 11 Configuration for 8-bit Y and Cb/Cr Input Video with TRS and Line Numbers
0
3
8-bit
LN0
LN1
XY
8
XY
00
00
00
00
Y, C b/Cr
V0
Video
EAV
SAV
Fig. 12 Video Input Format 8-bit with TRS and Line Numbers
Register Settings
NAME EXT_SEL DESCRIPTION 0: EXTH/EXTF output select 1: EXTH/EXTF input select 8BIT_SEL 0: 10-bit mode select 1: 8-bit mode select DSCBYPASS 0: Descrambling enabled 1: Bypass descrambling 0 1 0 1 1 0 ADDRESS 001 BIT 3 SETTING 0 DEFAULT 0
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Vn
FF
FF
1.3.3
10-bit or 8-bit Y and Cb/Cr Input without TRS and Line Numbers
The GS1503 will insert TRS and Line Numbers based on EXTF and EXTH inputs. See Figure 14 for timing. In progressive format video standards, a high-to-low edge signal must be input at the EXTF external pin on every frame to indicate the position of line 1. See Figure 15.
GS1503
GS1503 Y[9:0] VIN[19:10]
C b / Cr [9:0] EXTF EXTH +3.3V
VIN[9:0]
DSCBYPASS
Fig. 13 Configuration for 10-bit or 8-bit Y and Cb/Cr Input Video without TRS and Line Numbers
0
3
8/10-bit
8
Y, Cb /C r
V0
Video
4 VCLK EXTH
EXTF
Fig. 14 Video Input Format (8/10-bit without TRS and Line Numbers)
0
3
8/10-bit
8
Vn
Y, C b/C r
V0
Video
4 VCLK EXTH
EXTF Line 1
Fig. 15 Video Input Format (Progressive)
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Vn
Register Settings
NAME EXT_SEL DESCRIPTION 0: EXTH/EXTF output select 1: EXTH/EXTF input select 8BIT_SEL 0: 10-bit mode select 1: 8-bit mode select 1 0 or 1 0 ADDRESS 001 BIT 3 SETTING 1 DEFAULT 0
GS1503
DSCBYPASS
0: Descrambling enabled 1: Bypass descrambling
0
1
0
1.3.4 20-bit Scrambled Input
GS1503 Y/C b / Cr [19:0] VIN[19:0]
DSCBYPASS
Fig. 16 Configuration for 20-bit Scrambled Input
Register Settings (Default Mode)
NAME EXT_SEL DESCRIPTION 0: EXTH/EXTF output select 1: EXTH/EXTF input select 8BIT_SEL 0: 10-bit mode select 1: 8-bit mode select DSCBYPASS 0: Descrambling enabled 1: Bypass descrambling 0 0 0 1 0 0 ADDRESS 001 BIT 3 SETTING 0 DEFAULT 0
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1.4 VIDEO OUTPUT FORMAT 1.4.1 20-bit Scrambled Output
GS1503 Y/Cb / C r [19:0]
VOUT[19:0]
GS1503
SCRBYPASS
Fig. 17 Configuration for 20-bit Scrambled Output
Register Settings (Default Mode)
NAME SCRBYPASS DESCRIPTION 0: SMPTE 292M scrambling enabled 1: Bypass SMPTE 292M scrambling ADDRESS 001 BIT 2 SETTING 0 DEFAULT 0
1.4.2 10-bit Y and Cb/Cr Output
GS1503 Y[9:0] VOUT[19:10]
VOUT[9:0]
C b / Cr [9:0]
+3.3V
SCRBYPASS
Fig. 18 Configuration for 10-bit Y and Cb/Cr Output
Register Settings
NAME SCRBYPASS DESCRIPTION 0: SMPTE 292M scrambling enabled 1: Bypass SMPTE 292M scrambling ADDRESS 001 BIT 2 SETTING 1 DEFAULT 0
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1.5 VIDEO DATA PROCESSING 1.5.1 Video Signal Input Detection
The GS1503 will set the VIDEO_DET external pin HIGH when three consecutive TRS are detected in the input video signal. Also, the VIDEO_DET bit of Host Interface register 000h is set HIGH.
GS1503
Register Settings
NAME VIDEO_DET DESCRIPTION Video input signal detection (1: Detection) ADDRESS 000 BIT 6 SETTING DEFAULT 0
1.5.2 Video Input CRC Error Detection
The GS1503 will set the CRC_ERR external pin HIGH when a CRC error is detected in the input video signal. Also, the CRC_ERR bit 5 of Host Interface register 000h is set HIGH. The number of CRC errors accumulated in one video frame can be read form CRC_CNT[11:0] in Host Interface registers 006h and 007h.
Register Settings
NAME CRC_ERR CRC_CNT[11:0] DESCRIPTION Video input signal CRC error detection (1: Detection) Video input signal CRC error accumulation in 1 video frame ADDRESS 000 006 007 BIT 5 3-0 7-0 SETTING DEFAULT 0 0
1.5.3 Video Output CRC Insertion
When the CRC_INS bit 4 of Host Interface register 000h is set HIGH, the GS1503 will re-calculate the video line CRC words. The re-calculated CRC words are inserted in the video output signal. When CRC_INS is set LOW, the line CRC words are not updated and existing CRC words at the input of the device will be output unchanged.
Register Settings
NAME CRC_INS DESCRIPTION Video line CRC insertion (1: Insertion) ADDRESS 000 BIT 4 SETTING 1 DEFAULT 1
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1.5.4 Illegal Code Re-mapping
When LIMIT_ON bit 4 of Host Interface register 008h is set HIGH, input video words between 000-003 are re-mapped to 004, and values between 3FC-3FF are re-mapped to 3FB. Valid only when the EXT_SEL bit 3 of Host Interface register 000h is set HIGH. Register Settings
NAME EXT_SEL DESCRIPTION 0: EXTH/EXTF output select 1: EXTH/EXTF input select LIMIT_ON Illegal code re-mapping (1: Enabled) 008 4 1 0 ADDRESS 001 BIT 3 SETTING 1 DEFAULT 0
GS1503
1.5.5 Input Blanking
When VBLK_INS bit 3 of Host Interface register 008h is set HIGH, the input video vertical blanking will be set to 040h for the Luma channel and 200h for the Chroma channel. When HBLK_INS bit 2 of Host Interface register 008h is set HIGH, the input video horizontal blanking will be set to 040h for the Luma channel and 200h for the Chroma channel. The TRS, line number and CRC words will also be set to blanking values. Register Settings
NAME VBLK_INS HBLK_INS DESCRIPTION Input vertical blanking (1: Enabled) Input horizontal blanking (1: Enabled)
The blanking function is performed at the output of the GS1503 video data stream. If the HBLK_INS bit is set HIGH, any multiplexed audio will be replaced with blanking codes.
ADDRESS 008
BIT 3 2
SETTING 1 1
DEFAULT 0 0
1.5.6 Line Number Insertion
When LN_INS bit 1 of Host Interface register 008h is set HIGH, the GS1503 will insert line numbers into the video data stream. When set LOW, existing line numbers will remain in the output video stream.
When EXT_SEL bit 3 of Host Interface register 001h is set HIGH, line numbers will be inserted based on the timing of EXTH and EXTF input signals.
Register Settings
NAME LN_INS DESCRIPTION Line number insertion (1: Enabled) ADDRESS 008 BIT 1 SETTING 1 DEFAULT 1
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1.5.7 TRS Word Insertion
When TRS_INS bit 0 of Host Interface register 008h is set HIGH, the GS1503 will insert TRS codes into the video data stream. When set LOW, existing TRS codes will remain in the output video stream. Register Settings
When EXT_SEL bit 3 of Host Interface register 001h is set HIGH, TRS codes will be inserted based on the timing of EXTH and EXTF input signals.
GS1503
NAME TRS_INS
DESCRIPTION TRS word insertion (1: Enabled)
ADDRESS 008
BIT 0
SETTING 1
DEFAULT 1
1.6 AUDIO DATA PROCESSING 1.6.1 Digital Audio Input Format
Table 3: Audio Input Formats
AM[1:0] 0 1 2 AUDIO INPUT FORMAT Serial audio input: 24-bit Left Justified; MSB first Serial audio input: 24-bit Right Justified; MSB last AES/EBU audio input
The GS1503 will accept two audio input formats, AES/EBU digital audio input and serial input, as listed in Table 3. Serial input can be formatted in the following two modes. See Figure 19: 24-bit Left Justified; MSB first 24-bit Right Justified; MSB last The audio input format is configured using the AM[1:0] external pins or via AM[1:0] bits 1-0 in Host Interface register 010h. To configure the audio input format via the Host Interface, AM_SEL bit 7 in Host Interface register 010h must be set HIGH. The GS1503 will default to the AM[1:0] external pin setting. Register Settings
NAME AM_SEL DESCRIPTION 0: External pin setting 1: Register setting AM[1:0] Audio input format selection (AM[1] is MSB)
ADDRESS 010
BIT 7
SETTING 1
DEFAULT 0
1-0
See Table 3
0
Channel 1 WCINA/WCINB MSB MODE0 23 LSB MODE1 0 MODE2 (AES/EBU) 34 24-bit Audio Sample Word Validity Bit User Data Bit Channel Status Bit Parity Bit 0 23 2728293031 0 34 0 MSB 23 LSB 0
Channel 2
0
23 2728293031 24-bit Audio Sample Word VUCP
Sync Preamble
Sync V U C P Preamble
Fig. 19 Audio Input Formats
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1.6.2 Digital Audio Input Timing 1.6.2.1 AES/EBU Format Input
A 6.144MHz (128fs) audio clock must be supplied to the ACLKA and ACLKB inputs. ACLKA is used to clock the AES/EBU digital audio signal for channels 1 to 4 (AIN1/2 and AIN3/4) into the device. ACLKB is used to clock the AES/EBU digital audio signal for channels 5 to 8 (AIN5/6 and AIN7/8) into the device. In AES/EBU input mode, the WCINB and WCINB external pins should be grounded. See Figure 20 for timing.
GS1503
GS1503 Y/C b / Cr [19:0]
VIN[19:0]
Audio Channels 1 & 2 Audio Channels 3 & 4 6.144MHz (128 fs)
AIN1/2 AIN3/4 ACLKA WCINA
Audio Channels 5 & 6 Audio Channels 7 & 8 6.144MHz (128 fs)
AIN5/6 AIN7/8 ACLKB WCINB
6.144MHz ACLKA/B
AIN1/2, AIN3/4 AIN5/6, AIN7/8
Fig. 20 AES/EBU Input Configuration and Timing
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1.6.2.2
Serial Audio Input Modes
A 6.144MHz (128fs) audio clock must be supplied to the ACLKA and ACLKB inputs. The GS1503 divides this clock by 2 to clock the 3.072MHz audio data. An audio word clock at 48kHz (fs) must also be supplied to the WCINA and WCINB inputs, as shown in Figure 21. The AUDIO_CS[183:0] bits in Host Interface registers 058h to 06Eh can be used to enter the 23 8-bit bytes of the Audio Channel Status Block, as defined in AES3-1992. NOTE: The CRC byte is generated internally by the GS1503. The GS1503 will default to Professional audio mode with 24-bit word length and emphasis off. See Table 9.
GS1503
GS1503 Y/C b / Cr [19:0]
VIN[19:0]
Audio Channels 1 & 2 Audio Channels 3 & 4 6.144MHz (128 fs) 48kHz (fs)
AIN1/2 AIN3/4 ACLKA WCINA
Audio Channels 5 & 6 Audio Channels 7 & 8 6.144MHz (128 fs) 48kHz (fs)
AIN5/6 AIN7/8 ACLKB WCINB
64 CLKs ACLKA/B
64 CLKs
WCINA/B
AIN1/2, AIN3/4 AIN5/6, AIN7/8
Fig. 21 Serial Audio Input Configuration and Timing
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1.6.3 Audio Clock Phase Locked Loop
Figure 22 shows the configuration for deriving the 6.144MHz audio clock in AES/EBU audio input mode. The GS1503 will internally synchronize the AES/EBU audio input to the corresponding ACLK, using the clock extracted from the AES/EBU bi-phase mark encoding. This configuration is not required for serial audio input modes. See the Reference Design Section 3 for circuit specifics.
GS1503
6.144MHz (128 fs)
GS1503 Y/C b / Cr [19:0]
VIN[19:0]
Audio Channels 1 & 2 Audio Channels 3 & 4
AIN1/2 AIN3/4 ACLKA PLLCNTA Low Pass Filter VCXO 24.576MHz /4
Audio Channels 5 & 6 Audio Channels 7 & 8
AIN5/6 AIN7/8 ACLKB PLLCNTB Low Pass Filter VCXO 24.576MHz /4
6.144MHz (128 fs)
Fig. 22 Block Diagram of GS1503 Audio Clock PLL 1.6.4 Audio Signal Input Detection
The audio input signal detect registers will be set HIGH in AES/EBU audio mode when the preamble of the audio input data is detected 3 times consecutively. In serial audio input mode, the GS1503 will set the audio input signal detect Register Settings
NAME AUD7/8_DET AUD5/6_DET AUD3/4_DET AUD1/2_DET DESCRIPTION
registers HIGH when a 48kHz word clock is detected at the corresponding inputs. Audio channels 1 to 4 will be set when WCINA is validated, and audio channels 5 to 8 when WCINB is validated. Host Interface register 010h, bits 6-3, report the individual audio channels pairs detected.
ADDRESS 010
BIT 6 5 4 3
SETTING -
DEFAULT 0 0 0 0
Ch7/8 Audio input signal detection (1:Detection) Ch5/6 Audio input signal detection (1:Detection) Ch3/4 Audio input signal detection (1:Detection) Ch1/2 Audio input signal detection (1:Detection)
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1.6.5 Audio Channel Status CRC Error Detection
In AES/EBU audio mode, the GS1503 will check the Channel Status CRC for errors. If any Channel Status CRC errors are detected in an AES/EBU audio input channel pair, the corresponding bit in Host Interface register 011h will be set HIGH. In serial audio input mode, the CRC error flags are always set LOW.
GS1503
Register Settings
NAME ACRC7/8_ERR DESCRIPTION Ch7/8 Audio Channel Status CRC error detection (1: Detection) ACRC5/6_ERR Ch5/6 Audio Channel Status CRC error detection (1: Detection) ACRC3/4_ERR Ch3/4 Audio Channel Status CRC error detection (1: Detection) ACRC1/2_ERR Ch1/2 Audio Channel Status CRC error detection (1: Detection) 0 0 1 0 2 0 ADDRESS 011 BIT 3 SETTING DEFAULT 0
1.6.6 Audio Input Parity Error Detection
In AES/EBU audio mode, the GS1503 will check for Audio Parity errors. If any Audio Parity errors are detected in an AES/EBU audio input channel pair, the corresponding bit in Host Interface register 012h will be set HIGH. In serial audio input mode, the Audio Parity error flags are always set LOW. Register Settings
NAME AP7/8_ERR AP5/6_ERR AP3/4_ERR AP1/2_ERR DESCRIPTION Ch7/8 Audio parity error detection (1: Detection) Ch5/6 Audio parity error detection (1: Detection) Ch3/4 Audio parity error detection (1: Detection) Ch1/2 Audio parity error detection (1: Detection) ADDRESS 012 BIT 3 2 1 0 SETTING DEFAULT 0 0 0 0
1.6.7 Audio Channel Status CRC Insert Function
When bits 7-4 of Host Interface register 011h are set HIGH, the GS1503 will re-calculate the Channel Status CRC word for the corresponding audio input channel pair. The recalculated Channel Status CRC word is multiplexed into the Register Settings
NAME ACRC7/8_INS ACRC5/6_INS ACRC3/4_INS ACRC1/2_INS DESCRIPTION
audio data packet as per SMPTE 299M. When bits 3-0 of Host Interface register 011h are set LOW, the Channel Status CRC word is not updated and the existing Channel Status CRC word will be multiplexed. In serial audio input mode, these registers should be set LOW.
ADDRESS 011
BIT 7 6 5 4
SETTING 1 1 1 1
DEFAULT 0 0 0 0
Ch7/8 Audio Channel Status CRC insertion (1: Insertion) Ch5/6 Audio Channel Status CRC insertion (1: Insertion) Ch3/4 Audio Channel Status CRC insertion (1: Insertion) Ch1/2 Audio Channel Status CRC insertion (1: Insertion)
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1.7 AUDIO DATA PACKETS 1.7.1 Audio Data Packet Structure
Figure 23 shows the structure of the audio data packets as defined in SMPTE 299M. The audio data packets are multiplexed into the Chroma channel of the video data stream. Table 4 lists the description of the individual audio data packet words. Note that the GS1503 will automatically generate certain audio data packet words.
User Data Words
GS1503
10-bit
ECC0
ECC1
ECC2
ECC3
ECC4
ECC5
Yes Yes Yes Yes Yes Yes
DBN
CH1
CH2
CH3
ADF
CH4
CLK
DID
DC
ECC Protected
Fig. 23 Audio Data Packet Structure
Table 4: Audio Data Packet Word Descriptions
NAME ADF NO OF WORDS 3 Ancillary Data Flag DESCRIPTION DATA 000h 3FFh 3FFh DID 1 Audio Group Data ID 2E7h 1E6h 1E5h 2E4h DBN DC CLK CH1 CH2 CH3 CH4 ECC0-5 CS 1 1 2 4 4 4 4 6 1 Data Block Number Data Count Audio Clock Phase Data Channel 1 audio data Channel 2 audio data Channel 3 audio data Channel 4 audio data Error correction code for lower 8 bits of first 24 words Checksum. Calculates the sum of lower 9 bits of 22 words from DID Repeat 1-255 218h See Table 5 in Section 1-7-2 AUTO-GENERATION
1.7.2 Audio Data Packet DID Setting
The audio group DID for audio input channels 1 to 4 (AIN1/ 2 and AIN3/4) is set in DATAIDA[1:0] bits 1-0 of Host Interface register 014h. The audio group DID for audio input channels 5 to 8 (AIN5/6 and AIN7/8) is set in DATAIDB[1:0] bits 3-2 of Host Interface register 014h. Table 5 shows the 2-bit Host Interface setting for the corresponding audio group DID.
When CASCADE is set LOW (external pin or register), the GS1503 will default to audio groups 1 and 2, where AIN1/2 and AIN3/4 will be multiplexed with audio group 1 DID, and AIN5/6 and AIN7/8 with audio group 2 DID.
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CS
Table 5: Audio Data Packet Group DID Host Interface Setting
AUDIO GROUP 1 2 3 4 10-BIT DATA 2E7h 1E6h 1E5h 2E4h HOST INTERFACE REGISTER SETTING (2-BIT) 11b 10b
GS1503
01b 00b
Register Settings (CASCADE set LOW)
NAME DATAIDA [1-0] DATAIDB [1-0] DESCRIPTION Ch1-4 Audio data packet DID setting Ch5-8 Audio data packet DID setting ADDRESS 014 BIT 1-0 3-2 SETTING See Table 5 DEFAULT 11b 10b
When CASCADE is set HIGH (external pin or register), the GS1503 will default to audio groups 3 and 4, where AIN1/2 and AIN3/4 will be multiplexed with audio group 3 DID, and AIN5/6 and AIN7/8 with audio group 4 DID. Register Settings (CASCADE set HIGH)
NAME DATAIDA [1-0] DATAIDB [1-0] DESCRIPTION Ch1-4 Audio data packet DID setting Ch5-8 Audio data packet DID setting ADDRESS 014 BIT 1-0 3-2 SETTING See Table 5 DEFAULT 01b 00b
1.7.3
Audio Channel Multiplex Enable
Multiplexing of individual audio channels is enabled using the CHACT[7:0] bits 7-0 of Host Interface register 013h. When set HIGH, the corresponding audio channel is multiplexed into the audio data packet in the Chroma video Register Settings
NAME CHACT7 CHACT6 CHACT5 CHACT4 CHACT3 CHACT2 CHACT1 CHACT0 DESCRIPTION Ch8 multiplex enable (1: Enabled) Ch7 multiplex enable (1: Enabled) Ch6 multiplex enable (1: Enabled) Ch5 multiplex enable (1: Enabled) Ch4 multiplex enable (1: Enabled) Ch3 multiplex enable (1: Enabled) Ch2 multiplex enable (1: Enabled) Ch1 multiplex enable (1: Enabled)
data stream. CHACT7 corresponds to audio input channel 8 and CHACT0 corresponds to audio input channel 1. When all bits are set LOW, no audio data packets will be multiplexed and the GS1503 will be in bypass mode.
ADDRESS 013
BIT 7 6 5 4 3 2 1 0
SETTING -
DEFAULT 1 1 1 1 1 1 1 1
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1.8 VIDEO SWITCHING LINE SETTING
The video switching point for field 1 and field 2 can be configured via the GS1503 Host Interface. The SW_LNA[12:0] register is used to configure the video switching line for field 1, and SW_LNB[12:0] to set video switching line for field 2. In progressive format video standards, only the SW_LNA[12:0] register is used. The default settings are line 7 for field 1 and line 569 for field 2 as defined in SMPTE 299M. The GS1503 will not multiplex any audio data packets in the line immediately after the video switching point. For example, with the default setting of line 7 field 1, there will be no audio data packets in line 8. The next packets will appear on line 9. Audio control packets will be multiplexed once per field, two lines after the video switching point (on line 9, using the previous example). Arbitrary data packets will not be multiplexed in the two lines following the video switching point . Register Settings
NAME SW_LNA[12:0] DESCRIPTION Video Field 1 switching point setting
NOTE: The SMPTE 299M standard defines the video switching point as lines 7 and 569. If the SW_LNA[12:0] and SW_LNB[12:0] registers are programmed with values other than lines 7 and 569, the output of the GS1503 is not guaranteed to be compatible with all HD audio demultiplex systems. With non-SMPTE 299M compliant switch line settings, the user should avoid inputting a video data stream to the GS1503, which already contains embedded audio data and control packets. For reliable operation, non-SMPTE 299M compliant video data streams with embedded audio should not be used in conjunction with the GS1503 in Multiplex Mode.
GS1503
ADDRESS 004 005
BIT 4-0 7-0 4-0 7-0
SETTING -
DEFAULT 7d
SW_LNB[12:0]
Video Field 2 switching point setting
002 003
-
569d
1.9 MULTIPLEX CASCADE MODE
Two GS1503 devices can be cascaded in series to allow up to 16 channels of audio to be multiplexed (only one device requires CASCADE to be set HIGH). Figure 24 shows the cascade architecture for a 16-channel system. To configure
the GS1503 for cascade mode, the CASCADE external pin or CASCADE bit 7 of Host Interface register 014h is set HIGH. When set HIGH, the GS1503 will default to audio groups 3 and 4. When set LOW, the GS1503 will default to audio groups 1 and 2.
GS1503 Y/Cb /Cr [19:0] VIN[19:0] VOUT[19:0] Y/C b /Cr [19:0] VIN[19:0]
GS1503 VOUT[19:0] Y/C b /C r [19:0]
Audio Group 1
Audio Channels 1 & 2 Audio Channels 3 & 4
AIN1/2 AIN3/4
Audio Group 3
Audio Channels 9 & 10 Audio Channels 11 & 12
AIN1/2 AIN3/4
Audio Group 2
Audio Channels 5 & 6 Audio Channels 7 & 8
AIN5/6 AIN7/8
Audio Group 4
Audio Channels 13 & 14 Audio Channels 15 & 16 +3.3V
AIN5/6 AIN7/8
CASCADE
CASCADE
Fig. 24 Multiplexing 16 Channels of Audio using Cascade Architecture
Register Settings
NAME CASCADE DESCRIPTION Cascade enable (1: Enabled) ADDRESS 014 BIT 7 SETTING 1 DEFAULT 0
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When CASCADE is set LOW, the GS1503 will multiplex audio data and control packets as shown in Figure 25 (NOTE: Only the Chroma channel of the video data stream is shown). Any existing audio data or control packets will be deleted and replaced with blanking data before the new packets are multiplexed. New packets are multiplexed immediately after the two video line CRC words.
When CASCADE is set HIGH, the GS1503 will multiplex the audio data and control packets immediately after the existing packets, as shown in Figure 26. Avoid multiplexing new ancillary data packets with the same audio group DID as existing packets.
GS1503
CRC
EAV
Blank (200 h )
Video Signal before GS1503 (no existing Audio Data Packets)
Audio Group 1
Audio Group 2
CRC
EAV
Blank (200h)
Video Signal before GS1503 (with existing Audio Data Packets)
Audio Group 1 (New)
Audio Group 2 (New)
CRC
EAV
Blank (200h )
Video Signal after GS1503 Insertion of Audio Groups 1 & 2 (CASCADE = 0)
Fig. 25
Audio Group 1
Audio Group 2
CRC
EAV
Blank (200h)
Video Signal before GS1503 (with existing Audio Data Packets)
Audio Group 1 (Old)
Audio Group 2 (Old)
Audio Group 3 (New)
Audio Group 4 (New)
CRC
EAV
Blank (200 h)
Video Signal after GS1503 Insertion of Audio Groups 3 & 4 (CASCADE = 1)
Fig. 26
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SAV
LN
SAV
LN
SAV
LN
SAV
LN
SAV
LN
The GS1503 assumes that the ancillary data space from the first blanking location to the SAV contains no ancillary data packets. Existing ancillary data packets must be contiguous from the beginning of the HANC space or the GS1503 will overwrite existing packets with blanking before multiplexing new packets. See Figure 27.
GS1503
Audio Group 1
Blank (200h)
Audio Group 2
CRC
EAV
Blank (200 h)
Video Signal before GS1503 (with space between EAV and existing Audio Data Packets)
Audio Group 3 (New)
Audio Group 4 (New)
CRC
EAV
Blank (200 h )
Video Signal after GS1503 Insertion of Audio Groups 3 & 4 (CASCADE = 1)
Fig. 27 1.10 AUDIO CONTROL PACKETS 1.10.1 Audio Control Packet Structure
Figure 28 shows the structure of the audio control packet as defined in SMPTE 299M. An audio control packet is multiplexed once per field in the Luma channel of the video data stream. Table 6 lists descriptions of the individual audio control packet words. The GS1503 will automatically generate certain audio control packet words.
User Data Words
DEL1-2
DEL3-4
10-bit
RSRV
DBN
RATE
ADF
ACT
DID
DC
Fig. 28 Audio Control Packet Structure
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CS
AF
SAV
LN
SAV
LN
Table 6: Audio Control Packet Word Descriptions
NAME ADF NO OF WORDS 3 Ancillary Data Flag DESCRIPTION DATA 000h 3FFh 3FFh DID 1 Audio Group Data ID 1E3h 2E2h 2E1h 1E0h DBN DC AF 1 1 1 Data Block Number Data Count Audio Frame Number 200h 10Bh Yes Yes 9-bit Host Interface Setting 4-bit Host Interface Setting CHACT[7:0] setting 26-bit Host Interface setting 26-bit Host Interface setting 18-bit Host Interface setting Yes See Table 7 in Section 1-10-2 AUTOGENERATION Yes
GS1503
RATE
1
Sampling Frequency
-
ACT DEL1-2
1 3
Active Channel Ch1/2 Delay Data
-
DEL3-4
3
Ch3/4 Delay Data
-
RSRV
2
Reserved Words
200h
CS
1
Checksum. Calculates the sum of lower 9 bits of 15 words from DID
-
1.10.2 Audio Control Packet DID Setting
To multiplex audio control packets for audio channels 1 to 4 (inputs AIN1/2 and AIN3/4), the CTRONA bit 2 of Host Interface register 02Fh must be set HIGH. To multiplex audio control packets for audio channels 5 to 8 (inputs AIN5/6 and AIN7/8), the CTRONB bit 2 of Host Interface register 020h must be set HIGH. The audio control packet group DID for audio input channels 1 to 4 is set in CTRIDA[1:0] bits 1-0 of Host Interface register 02Fh. The audio control packet group DID for audio input channels 5 to 8 is set in CTRIDB[1:0] bits 3-2 of Host Interface register 020h. Table 7 shows the 2-bit Host Interface setting for the corresponding audio control packet group DID. When CASCADE is set LOW (external pin or register), the GS1503 will default to audio groups 1 and 2, where the audio control packet for AIN1/2 and AIN3/4 will be multiplexed with group 1 DID, and AIN5/6 and AIN7/8 with group 2 DID.
Control packet data can be programmed corresponding registers in the Host Interface. Table 7: Audio Control Packet Group DID Host Interface Settings
AUDIO GROUP 1 2 3 4 10-BIT DATA 1E3h 2E2h 2E1h 1E0h
via
the
HOST INTERFACE REGISTER SETTING (2-BIT) 11b 10b 01b 00b
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Register Settings
NAME CTRONA DESCRIPTION Ch1-4 Audio control packet multiplex enable (1: Enabled) Ch1-4 Audio control packet DID set ADDRESS 02F BIT 2 SETTING 1 DEFAULT 1
CTRIDA[1:0]
1-0
See Table 7
11b
GS1503
AF_NOA[8:0]
Ch1-4 Audio frame number
030 031
0 7-0 3-1 0 -
0
RATEA[2:0] ASXA
Ch1-4 Sampling frequency data Ch1-4 Synchronization (0:Synchronous; 1: Non-synchronous)
032
0 0
DEL1-2A[25:0]
Ch1/2 Delay data
033 034 035 036
1-0 7-0 7-0 7-0 1-0 7-0 7-0 7-0 1-0 7-0 7-0 2
-
0
DEL3-4A[25:0]
Ch3/4 Delay data
037 038 039 03A
-
0
RSRVA[17:0]
Ch1-4 Reserved words
03B 03C 03D
-
0
CTRONB
Ch5-8 Audio control packet multiplex enable (1: Enabled) Ch5-8 Audio control packet DID set
020
1
1
CTRIDB[1:0]
1-0
See Table 7
10b
AF_NOB[8:0]
Ch5-8 Audio frame number
021 022
0 7-0 3-1 0
-
0
RATEB[2:0] ASXB
Ch5-8 Sampling frequency data Ch5-8 Synchronization (0:Synchronous; 1: Non-synchronous) Ch5/6 Delay data
023
-
0 0
DEL1-2B[25:0]
024 025 026 027
1-0 7-0 7-0 7-0 1-0 7-0 7-0 7-0 1-0 7-0 7-0
-
0
DEL3-4B[25:0]
Ch7/8 Delay data
028 029 02A 02B
-
0
RSRVB[17:0]
Ch5-8 Reserved words
02C 02D 02E
-
0
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1.11 ARBITRARY DATA PACKETS
The GS1503 can multiplex arbitrary data packets according to SMPTE 291M. Typically, this consists of linear time code (LTC), vertical interval time code (VITC) or other user data, which is multiplexed once per video field. The GS1503 has
two modes in which arbitrary data can be multiplexed into the Luma channel of the video data stream. A maximum of 255 user data words can be multiplexed in one packet. Figure 29 shows the structure of the arbitrary data packet. NOTE: Arbitrary data packets will not be multiplexed in the two lines following the video switching point (see Section 1.8).
GS1503
MSB
UDW0[100] UDW1[101] UDW2[102] UDW3[103] ADF
Not b8 Parity bit
UDW252[1FC] UDW253[1FD] UDW251[1FB] UDW254[1FE]
UDW254
SDID
DID
LSB
DC
User Data Words Contents set in Host Interface registers
Fig. 29 Arbitrary Data Packet Structure 1.11.1 Arbitrary Data Multiplexing In External Pin Mode
This is the default mode for multiplexing arbitrary data packets. The GS1503 will set the PKTENO external pin HIGH when arbitrary data can be input to the device. Two VCLK cycles after PKTENO goes HIGH, the user should set the PKTEN arbitrary packet enable pin HIGH. Two VCLK cycles after PKTEN is set HIGH, arbitrary data can be input at the PKT[7:0] bus. See Figure 30 for timing.
The user is required to enter the following arbitrary data: Data ID (DID), Secondary Data ID (SDID), Data Count (DC) and User Data Words (UDW: maximum of 255), via the PKT[7-0] pins. This GS1503 automatically generates the Ancillary Data Flag (ADF), Checksum (CS) and bit 8 (Parity Bit) and bit 9 (Not bit 8). The PKTENO pin will be set HIGH on all video lines except the two lines following the video switching point. For example, with the default setting of line 7 field 1, PKTENO will not be set HIGH on lines 8 and 9. The switching point is set in the SW_LNA[12:0] and SW_LNB[12:0] Host Interface registers for field 1 and field 2 respectively. See Section 1-8.
GS1503
Y/C / C [19:0] br
VIN[19:0]
Arbitrary Data Packet Timing PKTENO
Arbitrary Data Input Enable PKTEN Arbitrary Data PKT[7:0]
2 CLKs VCLK
2 CLKs
2 CLKs
2 CLKs
PKTENO
PKTEN
PKT[7:0]
Arbitrary Data
UDW250
UDW251
ADF
ADF
ADF
DID
DC
Packet
Automatically generated by the GS1503
Fig. 30 Arbitrary Data Packet Input Timing Diagram
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CS
Arbitrary
UDW252
UDW253
UDW0
UDW1
UDW2
UDW3
SDID
CS
1.11.2 Arbitrary Data Multiplexing in Host Interface Mode
To select this mode, set ARBITMODE bit 0 in Host Interface register 050h HIGH. In this mode, the DID, SDID, DC and User Data Words must be programmed via the corresponding Host Interface registers. Set the video line number for field 1 and field 2 in which the arbitrary data packets are to be multiplexed using the ARBITLINEA[11:0] and ARBITLINEB[11:0] Host Interface registers
respectively. The arbitrary data packet is multiplexed when ARBITON bit 1 in Host Interface register 050h is set HIGH. ARBITON should be set LOW during the programming of the arbitrary data packet in the Host Interface. ARBITLINEA[11:0] and ARBITLINEB[11:0] should not be set to the two line numbers following the line number set in the SW_LNA[12:0] and SW_LNB[12:0] Host Interface registers. For example, with the default setting of line 7 field 1, ARBITLINEA[11:0] should not be set to line 8 or 9.
GS1503
Register Settings
NAME ARBITON DESCRIPTION Arbitrary packet multiplex enable (1: Enabled) Valid only when ARBITMODE is HIGH ARBITMODE Arbitrary packet mode selection (0: External pin mode; 1: Host mode) ARBITDID[7-0] ARBITSDID[7-0] ARBITDC[7-0] ARBITLINEA[11:0] Arbitrary packet DID setting Arbitrary packet SDID setting Arbitrary packet DC setting Field 1 multiplexing line 051 052 053 054 055 ARBITLINEB[11:0] Field 2 multiplexing line 056 057 ARBITUDW Arbitrary packet UDW setting 100-1FE 7-0 7-0 7-0 3-0 7-0 3-0 7-0 7-0 0 0 0 0 0 0 0 1 0 ADDRESS 050 BIT 1 SETTING 1 DEFAULT 0
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Table 8: Multiplex Mode Host Interface Registers
CONTROL ITEM Video NAME VM_SEL DESCRIPTION Video input format (external pin/internal register) configuration select. When set LOW, the video input format is configured via the VM[3:0] pins. When set HIGH, the video input format is configured via the "VM[3:0]" bits. Video signal detection flag. Set HIGH when 3 consecutive TRS are detected in the input video signal. Video input signal CRC error detection. Set HIGH when a CRC error is detected in the input video signal. This register is refreshed on every video frame. Video CRC insertion. When set HIGH, the Luma and Chroma line CRC words are re-calculated and inserted into the output video signal. Video input format selection. See Table 2. Valid when "VM_SEL" is HIGH. External EXTH/EXTF input select. When set LOW, the EXTH and EXTF pins are configured as outputs. When set HIGH, the GS1503 will insert TRS and Line Numbers based on signals input at the EXTH and EXTF pins. Scramble processing bypass select. When set HIGH, the internal scrambler and NRZ(I) encoder is bypassed. NOTE: The status of the SCRBYPASS external pin is not updated in this register. The value programmed in this register is logical OR'd with the SCRBYPASS external pin setting. 8BIT_SEL DSCBYPASS 8-bit input selection. When set HIGH, the GS1503 will accept an 8-bit input video signal. Descramble process bypass select. When set HIGH, the internal SMPTE 292M descrambler is bypassed. NOTE: The status of the DSCBYPASS external pin is not updated in this register. The value programmed in this register is logical OR'd with the DSCBYPASS external pin setting. SW_LNB[12:0] Video Field 2 switching line setting. Designates the video switching point for field 2. The default line number is 569, as defined by SMPTE 299M. Video Field 1 switching line setting. Designates the video switching point for field 1. The default line number is 7, as defined by SMPTE 299M. CRC error accumulation. Reports the accumulated number of CRC errors in one video frame. Not used. Illegal code re-mapping select. When set HIGH, input video words between 000-003 are remapped to 004, and values between 3FC-3FF are re-mapped to 3FB. Valid only when "EXT_SEL" is set HIGH. Vertical blanking enable. When set HIGH, the output video vertical blanking will be set to 040h for the Luma channel and 200h for the Chroma channel. 002 003 004 005 006 007 008 4-0 7-0 4-0 7-0 3-0 7-0 7-5 4 R/W 0 0 R 0 R/W 7d R/W 569d 1 0 R/W R/W 0 0 001 ADDRESS 000 BIT 7 R/W R/W DEFAULT 0
GS1503
VIDEO_DET
6
R
0
CRC_ERR
5
R
0
CRC_INS
4
R/W
1
VM[3:0] EXT_SEL
3-0 3
R/W R/W
0 0
SCRBYPASS
2
R/W
0
SW_LNA[12:0]
CRC_CNT[11:0]
RSV LIMIT_ON
VBLK_INS
3
R/W
0
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Table 8: Multiplex Mode Host Interface Registers (Continued)
CONTROL ITEM NAME HBLK_INS DESCRIPTION Horizontal blanking enable. When set HIGH, the output video horizontal blanking, including TRS, line numbers and line CRC words, will be set to 040h for the Luma channel and 200h for the Chroma channel. NOTE: If blanking of line numbers and TRS words is required, LN_INS and TRS_INS must be set LOW. LN_INS Line insertion enable. When set HIGH, the GS1503 will insert line numbers into the video data stream. When set LOW, existing line numbers will remain in the output video stream. TRS insertion enable. When set HIGH, the GS1503 will insert TRS codes into the video data stream. When set LOW, existing TRS codes will remain in the output video stream. Audio input format (external pin/register) configuration select. When set LOW, the audio input format is configured via the AM[1:0] pins. When set HIGH, the audio input format is configured via the "AM[1:0]" bits. Ch7/8 audio input signal detection. When set HIGH, an audio signal has been detected at the AIN7/8 input pin. Ch5/6 audio input signal detection. When set HIGH, an audio signal has been detected at the AIN5/6 input pin. Ch3/4 audio input signal detection. When set HIGH, an audio signal has been detected at the AIN3/4 input pin. Ch1/2 audio input signal detection. When set HIGH, an audio signal has been detected at the AIN1/2 input pin. Not used. Audio input format select. See Table 3. Valid when "AM_SEL" is HIGH. 010 1 R/W 1 ADDRESS BIT 2 R/W R/W DEFAULT 0
GS1503
TRS_INS
0
R/W
1
Audio
AM_SEL
7
R/W
0
AUD7/8_DET
6
R
0
AUD5/6_DET
5
R
0
AUD3/4_DET
4
R
0
AUD1/2_DET
3
R
0
RSV AM[1:0]
2 1-0
R/W
0 0
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Table 8: Multiplex Mode Host Interface Registers (Continued)
CONTROL ITEM NAME ACRC7/8_INS DESCRIPTION Ch7/8 audio Channel Status CRC insertion. When set HIGH, the Ch7/8 audio input Channel Status CRC is re-calculated before being multiplexed into the Audio Data Packet. Valid only when AES/ EBU audio input format is selected. Ch5/6 audio Channel Status CRC addition. When set HIGH, the Ch5/6 audio input Channel Status CRC is re-calculated before being multiplexed into the Audio Data Packet. Valid only when AES/ EBU audio input format is selected. Ch3/4 audio Channel Status CRC addition. When set HIGH, the Ch3/4 audio input Channel Status CRC is re-calculated before being multiplexed into the Audio Data Packet. Valid only when AES/ EBU audio input format is selected. Ch1/2 audio Channel Status CRC addition. When set HIGH, the Ch1/2 audio input Channel Status CRC is re-calculated before being multiplexed into the Audio Data Packet. Valid only when AES/ EBU audio input format is selected. Ch7/8 audio Channel Status error detection. When set HIGH, a Channel Status CRC error has been detected in the Ch7/8 audio input. Valid only when AES/EBU audio input format is selected. Ch5/6 audio Channel Status error detection. When set HIGH, a Channel Status CRC error has been detected in the Ch5/6 audio input. Valid only when AES/EBU audio input format is selected. Ch3/4 audio Channel Status error detection. When set HIGH, a Channel Status CRC error has been detected in the Ch3/4 audio input. Valid only when AES/EBU audio input format is selected. Ch1/2 audio Channel Status error detection. When set HIGH, a Channel Status CRC error has been detected in the Ch1/2 audio input. Valid only when AES/EBU audio input format is selected. Ch7/8 audio parity error detection. When set HIGH, an audio parity error has been detected in the Ch7/8 audio input. Valid only when AES/EBU audio input format is selected. Ch5/6 audio parity error detection. When set HIGH, an audio parity error has been detected in the Ch5/6 audio input. Valid only when AES/EBU audio input format is selected. Ch3/4 audio parity error detection. When set HIGH, an audio parity error has been detected in the Ch3/4 audio input. Valid only when AES/EBU audio input format is selected. Ch1/2 audio parity error detection. When set HIGH, an audio parity error has been detected in the Ch1/2 audio input. Valid only when AES/EBU audio input format is selected. Audio Channel Status set. Valid in Serial Audio Input modes. Used to enter the 23 8-bit bytes of the Audio Channel Status Block, as defined in AES3-1992. NOTE: The CRC byte is generated internally by the GS1503. 058 : 06E 012 ADDRESS 011 BIT 7 R/W R/W DEFAULT 0
GS1503
ACRC5/6_INS
6
R/W
0
ACRC3/4_INS
5
R/W
0
ACRC1/2_INS
4
R/W
0
ACS7/8_ERR
3
R
0
ACS5/6_ERR
2
R
0
ACS3/4_ERR
1
R
0
ACS1/2_ERR
0
R
0
AP7/8_ERR
3
R
0
AP5/6_ERR
2
R
0
AP3/4_ERR
1
R
0
AP1/2_ERR
0
R
0
Audio Channel Status Block
AUDIO_CS[7:0] : AUDIO_CS [183:176]
7-0 : 7-0
R/W
See Table 9
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Table 8: Multiplex Mode Host Interface Registers (Continued)
CONTROL ITEM Audio Data Packet NAME CHACT[7-0] DESCRIPTION Audio channel multiplex enable. When set HIGH, the corresponding audio channel is multiplexed into the Chroma video data stream. "CHACT[7]" corresponds to audio input channel 8 and "CHACT[0]" corresponds to audio input channel 1. When all bits are set LOW, no audio data packets will be multiplexed and the GS1503 will be in bypass mode. Cascade select. When set HIGH, the GS1503 will default to audio groups 3 and 4. When set LOW, the GS1503 will default to audio groups 1 and 2. NOTE: The status of the CASCADE external pin is not updated in this register. The value programmed in this register is logical OR'd with the CASCADE external pin setting. RSV AMUTEB Not used. Ch5-8 audio mute enable. When set HIGH, the multiplexed audio packets for audio channels 5 to 8 are forced to zero. NOTE: The status of the MUTE external pin is not updated in this register. The value programmed in this register is logical OR'd with the MUTE external pin setting. AMUTEA Ch1-4 audio mute enable. When set HIGH, the multiplexed audio packets for audio channels 1 to 4 are forced to zero. NOTE: The status of the MUTE external pin is not updated in this register. The value programmed in this register is logical OR'd with the MUTE external pin setting. DATAIDB[1:0] Ch5-8 audio group DID setting. Designates the audio group DID for audio channels 5 to 8. See Table 5. When CASCADE (external pin or register) is set LOW, the default setting is audio group 2. When CASCADE is set HIGH, the default setting is audio group 4. Ch1-4 audio group DID setting. Designates the audio group DID for audio channels 1 to 4. See Table 5. When CASCADE (external pin or register) is set LOW, the default setting is audio group 1. When CASCADE is set HIGH, the default setting is audio group 3. Not used. Ch5-8 audio control packet multiplex enable. When set HIGH, the audio control packets for audio channels 5 to 8 will be multiplexed into the Luma channel of the video data stream. Ch5-8 audio control packet DID setting. Designates the audio control packet DID for audio channels 5 to 8. See Table 7. The default setting is audio group 2. 020 3-2 R/W 10b 4 R/W 0 6 5 R/W 0 ADDRESS 013 BIT 7-0 R/W R/W DEFAULT FFh
GS1503
CASCADE
014
7
R/W
0
DATAIDA[1:0]
1-0
R/W
11b
Audio Control Packet
RSV CTRONB
7-3 2
R/W
0 1
CTRIDB[1:0]
1-0
R/W
10b
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Table 8: Multiplex Mode Host Interface Registers (Continued)
CONTROL ITEM NAME AF_NOB[8:0] DESCRIPTION Ch5-8 audio frame number. Designates the audio frame number for audio channels 5 to 8. Will be multiplexed into the audio control packet as per SMPTE 299M. Ch5-8 sampling frequency set. Designates the audio sampling frequency for audio channels 5 to 8. Will be multiplexed into the RATE word of the audio control packet as per SMPTE 299M. The default setting is 48kHz. Ch5-8 synchronization set. When set HIGH, the "asx" bit of the audio control packet RATE word designates audio channels 5 to 8 as asynchronous, as per SMPTE 299M. When set LOW, the "asx" bit of the audio control packet RATE word designates synchronous audio (default setting). Ch5/6 delay data. Designates the accumulated audio processing delay relative to video for audio channels 5 and 6. Will be multiplexed into the audio control packet as per SMPTE 299M. Ch7/8 delay data. Designates the accumulated audio processing delay relative to video for audio channels 7 and 8. Will be multiplexed into the audio control packet as per SMPTE 299M. Ch5-8 reserve words. Designates the value set in the RSRV words of the audio control packet for audio channels 5 to 8, as per SMPTE 299M. NOTE: As these words are reserved for future use, they should be set to zero. RSV CTRONA Not used. Ch1-4 audio control packet multiplex enable. When set HIGH, the audio control packets for audio channels 1 to 4 will be multiplexed into the Luma channel of the video data stream. Ch1-4 audio control packet DID setting. Designates the audio control packet DID for audio channels 1 to 4. See Table 7. The default setting is audio group 1. Ch1-4 audio frame number. Designates the audio frame number for audio channels 5 to 8. Will be multiplexed into the audio control packet as per SMPTE 299M. Ch1-4 sampling frequency set. Designates the audio sampling frequency for audio channels 1 to 4. Will be multiplexed into the RATE word of the audio control packet as per SMPTE 299M. The default setting is 48kHz. Ch1-4 synchronization set. When set HIGH, the "asx" bit of the audio control packet RATE word designates audio channels 1 to 4 as asynchronous, as per SMPTE 299M. When set LOW, the "asx" bit of the audio control packet RATE word designates synchronous audio (default setting). 030 031 02F 7-3 2 R/W 0 1 024 025 026 027 028 029 02A 02B 02C 02D 02E ADDRESS 021 022 BIT 0 7-0 R/W R/W DEFAULT 0
RATEB[2:0]
023
3-1
R/W
0
GS1503
ASXB
0
R/W
0
DEL1-2B[25:0]
1-0 7-0 7-0 7-0 1-0 7-0 7-0 7-0 1-0 7-0 7-0
R/W
0
DEL3-4B[25:0]
R/W
0
RSRVB[17:0]
R/W
0
CTRIDA[1:0]
1-0
R/W
11b
AF_NOA[8:0]
0 7-0
R/W
0
RATEA[2:0]
032
3-1
R/W
0
ASXA
0
R/W
0
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Table 8: Multiplex Mode Host Interface Registers (Continued)
CONTROL ITEM NAME DEL1-2A[25:0] DESCRIPTION Ch1/2 delay data. Designates the accumulated audio processing delay relative to video for audio channels 1 and 2. Will be multiplexed into the audio control packet as per SMPTE 299M. Ch3/4 delay data. Designates the accumulated audio processing delay relative to video for audio channels 3 and 4. Will be multiplexed into the audio control packet as per SMPTE 299M. Ch1-4 reserve words. Designates the value set in the RSRV words of the audio control packet for audio channels 1 to 4, as per SMPTE 299M. NOTE: As these words are reserved for future use, they should be set to zero. Arbitrary Data Packet ARBITON Arbitrary data packet multiplex. Valid only when "ARBITMODE" is HIGH. When set HIGH, arbitrary data packets will be multiplexed into the Luma video data stream using the Host Interface register settings. Arbitrary packet mode select. When set HIGH, arbitrary data packets are multiplexed using the Host Interface register settings. When set LOW, arbitrary data packets are multiplexed using the external pin inputs. Arbitrary packet Data ID setting. Designates the 8 LSBs of the arbitrary data packet DID word. The 2 MSBs are internally generated. "ARBITDID[7]" is the MSB and "ARBITDID[0]" is the LSB. Valid only when "ARBITMODE" is HIGH. Arbitrary packet Secondary Data ID setting. Designates the 8 LSBs of the arbitrary data packet secondary DID word. The 2 MSBs are internally generated. "ARBITSDID[7]" is the MSB and "ARBITSDID[0]" is the LSB. Valid only when "ARBITMODE" is HIGH. Arbitrary packet DC setting. Designates the 8 LSBs of the arbitrary data packet Data Count word. The 2 MSBs are internally generated. "ARBITDC[7]" is the MSB and "ARBITDC[0]" is the LSB. Valid only when "ARBITMODE" is HIGH. Field 2 arbitrary packet multiplex line number setting. Designates the field 2 video line in which the arbitrary data packets will be multiplexed. Valid only when "ARBITMODE" is HIGH. Field 1 arbitrary packet multiplex line number setting. Designates the field 1 video line in which the arbitrary data packets will be multiplexed. Valid only when "ARBITMODE" is HIGH. Arbitrary packet User Data Word set. Designates the 8 LSBs for each of the 255 arbitrary packet User Data Words. The 2 MSBs are internally generated. Valid only when "ARBITMODE" is HIGH. 051 050 1 R/W 0 ADDRESS 033 034 035 036 037 038 039 03A 03B 03C 03D BIT 1-0 7-0 7-0 7-0 1-0 7-0 7-0 7-0 1-0 7-0 7-0 R/W 0 R/W 0 R/W R/W DEFAULT 0
DEL3-4A[25:0]
GS1503
RSRVA[17:0]
ARBITMODE
0
R/W
0
ARBITDID[7:0]
7-0
R/W
0
ARBITSDID[7:0]
052
7-0
R/W
0
ARBITDC[7:0]
053
7-0
R/W
0
ARBITLINEB[11:0]
054 055
3-0 7-0
R/W
0
ARBITLINEA[11:0]
056 057
3-0 7-0
R/W
0
ARBITUDW0 : ARBITUDW254
100 : 1FE
7-0 : 7-0
R/W
0
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Table 9: Audio Channel Status Default Values
ADDRESS 058 059 05A Others VALUE 85 08 2C 00 CHANNEL STATUS Professional; Valid Audio; No Emphasis (manual override disabled); 48kHz Sampling Frequency (manual override disabled). Two-Channel Mode (manual override disabled). Maximum Audio Sample Word Length is 24bits; Encoded Audio Word Length is 24-bit. -
GS1503
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2. DEMULTIPLEX MODE
2.1 FUNCTIONAL OVERVIEW
The GS1503 HD Embedded Audio CODEC fully supports the demultiplexing of Audio Data Packets, Audio Control Packets and Arbitrary Data Packets as per SMPTE 291M and 299M. The device can be configured to operate with all video standards defined in SMPTE 292M, levels A through M. The GS1503 also supports the 1080/24PsF, 25PsF and 30PsF video formats as described in SMPTE RP211. The video input format can be one of the following configurations: 10-bit Y and Cb/Cr input with TRS and Line Numbers 20-bit scrambled input The video output format can be one of the following configurations: 20-bit scrambled output 10-bit Y and Cb/Cr output Up to a maximum of 8 channels of 48kHz digital audio can be demultiplexed per device. The audio output format can be selected as either AES/EBU, or one of two serial audio data output modes. A maximum of 16 channels of audio can be demultiplexed by cascading two devices in parallel.
Audio control packets, as defined in SMPTE 299M, can also be demultiplexed to obtain information about the nature of the embedded audio data. The contents of the audio control packet are stored in registers of the Host Interface. The GS1503 will also demultiplex arbitrary data packets as defined in SMPTE 291M. The arbitrary data packets can serve as an auxiliary data signal for proprietary applications. The GS1503 can be configured to demultiplex arbitrary data packets and output them at dedicated external pins or via the Host Interface registers. Up to a maximum of 255 8-bit words can be demultiplexed (excluding Ancillary Data Flags and Checksum). To use the GS1503 in Demultiplex Mode, set the MUX/DEMUX external pin HIGH.
2.2 VIDEO STANDARD
GS1503
The video standard is selected from the VM[3:0] external pins or VM[3:0] bits 3-0 in Host Interface register 000h. To configure the video standard via the Host Interface, VM_SEL bit 7 in Host Interface register 000h must be set HIGH. The GS1503 will default to the VM[3:0] external pin setting. The supported video standards are listed in Table 10.
. Table 10: Supported Video Standards
VM [3:0] 1110b 1100b 1000b 1010b 1111b 0010b 0100b 0110b 0000b 0001b 0011b 0101b 0111b INPUT FORMAT 1035i (30 & 30/1.001 Hz) 1080i (25 Hz) 1080i/1080sF (30 & 30/1.001 Hz) 1080i/1080sF (25 Hz) 1080sF (24 & 24/1.001 Hz) 1080p (30 & 30/1.001 Hz) 1080p (25 Hz) 1080p (24 & 24/1.001 Hz) 720p (60 & 60/1.001 Hz) 720p (30 & 30/1.001 Hz) 720p (50 Hz) 720p (25 Hz) 720p (24 & 24/1.001 Hz) All other settings are reserved REFERENCE SMPTE DOCUMENT 260M 295M 274M, RP211 274M, RP211 RP211 274M 274M 274M 296M 296M 296M 296M 296M G, H I J, K L, M SMPTE 292M LEVEL A, B C D, E F
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Register Settings
NAME VM_SEL DESCRIPTION 0: External pin select 1: Register select VM[3:0] Video formal selection (VM[3] is MSB) 3-0 See Table 10 0 ADDRESS 000 BIT 7 SETTING 1 DEFAULT 0
GS1503
2.3 VIDEO INPUT FORMAT 2.3.1 20-bit Scrambled Input
GS1503 Y/C b / Cr [19:0]
VIN[19:0]
DSCBYPASS
Fig. 31 20-bit Scrambled Input Configuration
Register Settings (Default Mode)
NAME EXT_SEL DESCRIPTION 0: EXTH/EXTF output select 1: EXTH/EXTF input select 8BIT_SEL 0: 10-bit mode select 1: 8-bit mode select DSCBYPASS 0: Descrambling enabled 1: Bypass descrambling 0 0 0 1 0 0 ADDRESS 001 BIT 3 SETTING 0 DEFAULT 0
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2.3.2 10-bit Y and Cb/Cr Input with TRS and Line Numbers
GS1503 Y[9:0] VIN[19:10]
C b/ C r[9:0]
VIN[9:0]
GS1503
EXTF +3.3V EXTH
DSCBYPASS
Fig. 32 10-bit Y and Cb/Cr Input with TRS and Line Numbers Configuration
0
3
10-bit
CRC0
CRC1
LN0
LN1
000
000
8
XYZ
000
000
XYZ
3FF
3FF
V0
Y, C b / Cr
Video
4 VCLK EXTH
EXTF
Fig. 33 Video Input Format (10-bit with TRS and Line Numbers)
Register Settings
NAME EXT_SEL DESCRIPTION 0: EXTH/EXTF output select 1: EXTH/EXTF input select 8BIT_SEL 0: 10-bit mode select 1: 8-bit mode select DSCBYPASS 0: Descrambling enabled 1: Bypass descrambling 0 1 0 1 0 0 ADDRESS 001 BIT 3 SETTING 0 DEFAULT 0
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Vn
2.4 VIDEO OUTPUT FORMAT 2.4.1 10-bit Y and Cb/Cr Output
GS1503 Y[9:0] VOUT[19:10]
GS1503
VOUT[9:0]
C b / C r [9:0]
+3.3V
SCRBYPASS
Fig. 34 10-bit Y and Cb/Cr Output Configuration
Register Settings
NAME SCRBYPASS DESCRIPTION 0: SMPTE 292M scrambling enabled 1: Bypass SMPTE 292M scrambling ADDRESS 001 BIT 2 SETTING 1 DEFAULT 0
2.4.2 20-bit Scrambled Output
GS1503 Y/C b / Cr [19:0]
VOUT[19:0]
SCRBYPASS
Fig. 35 20-bit Scrambled Output Configuration
Register Settings (Default Mode)
NAME SCRBYPASS DESCRIPTION 0: SMPTE 292M scrambling enabled 1: Bypass SMPTE 292M scrambling ADDRESS 001 BIT 2 SETTING 0 DEFAULT 0
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2.5 VIDEO DATA PROCESSING 2.5.1 Video Signal Input Detection
The GS1503 will set the VIDEO_DET external pin HIGH when three consecutive TRS are detected in the input video signal. Also, the VIDEO_DET bit of Host Interface register 000h is set HIGH.
GS1503
Register Settings
NAME VIDEO_DET DESCRIPTION Video input signal detection (1: Detection) ADDRESS 000 BIT 6 SETTING DEFAULT 0
2.5.2 Video Input CRC Error Detection
The GS1503 will set the CRC_ERR external pin HIGH when a CRC error is detected in the input video signal. Also, the CRC_ERR bit 5 of Host Interface register 000h is set HIGH. The number of CRC errors accumulated in one video frame can be read form CRC_CNT[11:0] in Host Interface registers 006h and 007h. Register Settings
NAME CRC_ERR CRC_CNT[11:0] DESCRIPTION Video input signal CRC error detection (1: Detection) Video input signal CRC error accumulation in 1 video frame ADDRESS 000 006 007 BIT 5 3-0 7-0 SETTING DEFAULT 0 0
2.5.3 Video Output CRC Insertion
When the CRC_INS bit 4 of Host Interface register 000h is set HIGH, the GS1503 will re-calculate the video line CRC words. The re-calculated CRC words are inserted in the video output signal. When CRC_INS is set LOW, the line CRC words are not updated and existing CRC words at the input of the device will be output unchanged. Register Settings
NAME CRC_INS DESCRIPTION Video line CRC insertion (1: Insertion) ADDRESS 000 BIT 4 SETTING 1 DEFAULT 1
2.5.4 Input Blanking
When VBLK_INS bit 3 of Host Interface register 008h is set HIGH, the input video vertical blanking will be set to 040h for the Luma channel and 200h for the Chroma channel. When HBLK_INS bit 2 of Host Interface register 008h is set HIGH, the input video horizontal blanking will be set to 040h for the Luma channel and 200h for the Chroma channel. The TRS, line number and CRC words will also be set to blanking values.
The blanking function is performed at the output of the GS1503 video data stream. If the HBLK_INS bit is set HIGH, any embedded audio or control packets will be replaced with blanking codes. The GS1503 will demultiplex data contained in the packets, prior to the blanking function, and output at the corresponding pins.
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Register Settings
NAME VBLK_INS HBLK_INS DESCRIPTION Input vertical blanking (1: Enabled) Input horizontal blanking (1: Enabled) ADDRESS 008 BIT 3 2 SETTING 1 1 DEFAULT 0 0
2.5.5 Line Number Insertion
GS1503
When LN_INS bit 1 of Host Interface register 008h is set HIGH, the GS1503 will insert line numbers into the video data stream. When set LOW, existing line numbers will remain in the output video stream. Register Settings
NAME LN_INS DESCRIPTION Line number insertion (1: Enabled) ADDRESS 008 BIT 1 SETTING 1 DEFAULT 1
2.5.6 TRS Word Insertion
When TRS_INS bit 0 of Host Interface register 008h is set HIGH, the GS1503 will insert TRS codes into the video data stream. When set LOW, existing TRS codes will remain in the output video stream. Register Settings
NAME TRS_INS DESCRIPTION TRS word insertion (1: Enabled) ADDRESS 008 BIT 0 SETTING 1 DEFAULT 1
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2.6 AUDIO DATA PROCESSING 2.6.1 Digital Audio Output Format
Table 11: Audio Output Formats
AM[1:0] 0 1 2 AUDIO OUTPUT FORMAT Serial audio output: 24-bit Left Justified; MSB first Serial audio output: 24-bit Right Justified; MSB last AES/EBU audio output
The GS1503 has two audio output formats, AES/EBU digital audio output and serial output, as listed in Table 11. The serial audio output can be formatted in the following two modes. See Figure 36: 24-bit Left Justified; MSB first 24-bit Right Justified; MSB last The audio output format is configured using the AM[1:0] external pins or via AM[1:0] bits 1-0 in Host Interface register 010h. To configure the audio output format via the Host Interface, AM_SEL bit 7 in Host Interface register 010h must be set HIGH. The GS1503 will default to the AM[1:0] external pin setting. NOTE: When configured in AES/EBU audio mode, the GS1503 will not output a 48kHz (fs) word clock at the WCOUTA and WCOUTB pins.
GS1503
Register Settings
NAME AM_SEL DESCRIPTION 0: External pin setting 1: Register setting AM[1:0] Audio output format selection (AM[1] is MSB) 1-0 See Table 11 0 ADDRESS 010 BIT 7 SETTING 1 DEFAULT 0
WCOUTA/WCOUTB MSB MODE0 23 LSB MODE1 0 MODE2 (AES/EBU) 34 0
Channel 1 MSB 0 23 LSB 23 2728293031 0 24-bit Audio Sample Word Validity Bit User Data Bit Channel Status Bit Parity Bit 34 0
Channel 2
0
23 2728293031 24-bit Audio Sample Word VUCP
Sync Preamble
Sync V U C P Preamble
Fig. 36 Audio Output Formats
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2.6.2 Digital Audio Output Timing 2.6.2.1 AES/EBU Format Output
A 6.144MHz (128fs) audio clock must be supplied to the ACLKA and ACLKB inputs. ACLKA is used to clock AES/ EBU digital audio signal for channels 1 to 4 (AOUT1/2 and AOUT3/4). ACLKB is used to clock AES/EBU digital audio signal for channels 5 to 8 (AOUT5/6 and AOUT7/8). In AES/ EBU output mode, the audio word clock inputs WCINB and WCINB should be grounded. See Figure 37 for timing. The user can access the Audio Channel Status Block information via the AUDIO_CS[183:0] bits in Host Interface registers 058h to 06Eh. To read the Audio Channel Status information, the CS_MODE bit 3 of Host Interface register 06Fh should be set HIGH. The embedded audio channel Register Settings
NAME CS_WEND DESCRIPTION Audio Channel Status write flag (1: Data ready) CS_RQST Audio Channel Status request (1: enable) CS_MODE 0: Audio Channel Status replace 1: Audio Channel Status demultiplex CH_SEL[2:0] Audio Channel Status select
from which the Channel Status information is to be extracted is set in the CH_SEL[2:0] bits 2-0 of Host Interface register 06Fh. The CH_SEL[2:0] setting for audio channel 1 is 000b, through to 111b for channel 8. The CS_RQST bit must be set HIGH to begin the process of extracting the Audio Channel Status information. Once extracted, the GS1503 will set CS_WEND bit HIGH and the user can access the data for Host Interface registers 058h to 06Eh. When CS_MODE is set LOW, the Audio Channel Status information in the AES/EBU audio outputs will be replaced with data programmed in the AUDIO_CS[183:0] bits of Host Interface registers 058h to 06Eh.
GS1503
ADDRESS 06F
BIT 5
SETTING -
DEFAULT 0
4
1
0
3
1
0
2-0
-
000b
GS1503 Y/C b / Cr [19:0]
VIN[19:0]
AOUT1/2 AOUT3/4 6.144MHz (128 fs) ACLKA
Audio Channels 1 & 2 Audio Channels 3 & 4
AOUT5/6 AOUT7/8 6.144MHz (128 fs) ACLKB
Audio Channels 5 & 6 Audio Channels 7 & 8
6.144MHz ACLKA/B
AOUT1/2, AOUT3/4 AOUT5/6, AOUT7/8
Fig. 37 AES/EBU Audio Output Configuration and Timing
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2.6.2.2
Serial Audio Output Modes
A 6.144MHz (128fs) audio clock must be supplied to the ACLKA and ACLKB inputs. An audio word clock at 48kHz (fs) will be output at the WCOUTA and WCOUTB external pins, as shown in Figure 38. The user can access the Audio Channel Status Block information via the AUDIO_CS[183:0] bits in Host Interface registers 058h to 06Eh. To read the Audio Channel Status information, the CS_MODE bit 3 of Host Interface register 06Fh should be set HIGH. The embedded audio channel from which the Channel Status information is to be extracted is set in the CH_SEL[2:0] bits 2-0 of Host Interface register 06Fh. The CH_SEL[2:0] setting for audio channel 1 is 000b, through to 111b for channel 8.
GS1503 Y/C b / Cr [19:0]
The CS_RQST bit must be set HIGH to begin the process of extracting the Audio Channel Status information. Once extracted, the GS1503 will set CS_WEND bit HIGH and the user can access the data for Host Interface registers 058h to 06Eh. When DEC_MODE (external pin or register setting) is set LOW, the audio word clock inputs WCINB and WCINB should be grounded.
GS1503
VIN[19:0]
AOUT1/2 AOUT3/4 6.144MHz (128 fs) ACLKA WCOUTA
Audio Channels 1 & 2 Audio Channels 3 & 4 48kHz (fs)
AOUT5/6 AOUT7/8 6.144MHz (128 fs) ACLKB WCOUTB
Audio Channels 5 & 6 Audio Channels 7 & 8 48kHz (fs)
64 CLKs ACLKA/B
64 CLKs
WCOUTA/B
AOUT1/2, AOUT3/4 AOUT5/6, AOUT7/8
Fig. 38 Serial Audio Output Configuration and Timing
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2.6.3 Audio Clock Phase Locked Loop
Figure 39 shows the configuration for deriving the 6.144MHz audio clock in AES/EBU and serial audio output modes. The GS1503 will internally synchronize the audio output to the corresponding ACLK. This configuration is not required when DEC_MODE is set HIGH. See the Reference Design Section 3 for circuit specifics.
GS1503
6.144MHz (128 fs)
GS1503 Y/C b / C r [19:0]
VIN[19:0] AOUT1/2 AOUT3/4 Audio Channels 1 & 2 Audio Channels 3 & 4
Low ACLKA PLLCNTA Pass Filter Audio Channels 5 & 6 Audio Channels 7 & 8
VCXO 24.576MHz
/4
AOUT5/6 AOUT7/8
Low ACLKB PLLCNTB Pass Filter
VCXO 24.576MHz
/4
6.144MHz (128 fs)
Fig. 39 Block Diagram of GS1503 Audio Clock PLL 2.6.4 Audio Data Packet Detection
The audio data packet detect registers will be set HIGH when a corresponding audio group DID has been detected in the Chroma channel of the input video stream. Host Interface register 013h, bits 7-4, report the individual audio groups detected. Register Settings
NAME ADPG4_DET ADPG3_DET ADPG2_DET ADPG1_DET DESCRIPTION Audio group 4 data packet detection (1:Detection) Audio group 3 data packet detection (1:Detection) Audio group 2 data packet detection (1:Detection) Audio group 1 data packet detection (1:Detection) ADDRESS 013 BIT 7 6 5 4 SETTING DEFAULT 0 0 0 0
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2.6.5 ECC Error Detection & Correction
The GS1503 performs BCH(31,25) forward error detection and correction as described in SMPTE 299M. The error correction for audio data packets with audio group DID set in DATAIDA[1:0] is activated when ECCA_ON bit 0 of Host Interface register 013h is set HIGH. Similarly, error correction for audio data packets with audio group DID set in DATAIDB[1:0] is activated when ECCB_ON bit 1 of Host Interface register 013h is set HIGH When a one-bit error is detected in a bit array of the ECC protected region of the audio data packet with audio group DID set in DATAIDA[1:0], ECCA_ERR bit 1 in Host Interface register 015h is set HIGH. When a one-bit error is detected in the ECC protected region of the audio data packet with audio group DID set in DATAIDB[1:0], the ECCB_ERR bit 5 in Host Interface register 015h is set HIGH. In both cases, the ERROR external pin will also be set HIGH. Register Settings
NAME ECCB_ERR DESCRIPTION
A bit array is defined as all 24 bits of bit 0. The next bit array is all 24 bits of bit 1, and so on through to bit 7. Up to 8 bits in error can be corrected, providing each bit error is in a different bit array. When there are two bits in error in the same 24-bit array, the errors will be detected, but not corrected. When there are more than two bits in error in a single bit array, the errors will not be detected or corrected.
GS1503
The number of audio data packets corrected in one video frame will be reported in the corresponding Host Interface registers CORRECTA[11:0] and CORRECTB[11:0]. The GS1503 will also report the number of audio data packets which could not be corrected in one video frame in the corresponding Host Interface registers NO_CORRECTA[11:0] and NO_CORRECTB[11:0].
ADDRESS 015
BIT 5
SETTING -
DEFAULT 0
Ch5-8 Audio data packet ECC error detection (1: Detection)
ECCA_ERR
Ch1-4 Audio data packet ECC error detection (1: Detection)
1
-
0
CORRECTB[11:0]
Ch5-8 correctable packets in one video frame
016 017
3-0 7-0 3-0 7-0 3-0 7-0 3-0 7-0 1 0
-
0
NO_CORRECTB[11:0]
Ch5-8 un-correctable packets in one video frame
018 019
-
0
CORRECTA[11:0]
Ch1-4 correctable packets in one video frame
01A 01B
-
0
NO_CORRECTA[11:0]
Ch5-8 un-correctable packets in one video frame
01C 01D
-
0
ECCB_ON ECCA_ON
Ch5-8 Audio data packet error correction (1: ON) Ch1-4 Audio data packet error correction (1: ON)
013
1 1
1 1
2.6.6 Audio Data Packet Error Detection
When the 1-255 count sequence in the Data Block Number (DBN) word of audio data packets with audio group DID set in DATAIDA[1:0] is discontinuous, the DBNA_ERR bit 3 of Host Interface register 015h will be set HIGH. When the1255 count sequence in the DBN word of audio data packets with audio group DID set in DATAIDB[1:0] is discontinuous, the DBNB_ERR bit 7 of Host Interface register 015h will be set HIGH. The GS1503 will check the parity (bit 8) for the CLK, CH1-4 and ECC0-5 words in the embedded audio data packets. When a parity bit error is detected in audio data packets with audio group DID set in DATAIDA[1:0], the ADPB8A_ERR bit 2 of Host Interface register 015h will be
set HIGH. When a parity bit error is detected in audio data packets with audio group DID set in DATAIDB[1:0], the ADPB8B_ERR bit 6 of Host Interface register 015h will be set HIGH. The GS1503 will re-calculate the audio data packets Checksum and compare against the embedded Checksum word. When a Checksum error is detected in audio data packets with audio group DID set in DATAIDA[1:0], the ADPCSA_ERR bit 0 of Host Interface register 015h will be set HIGH. When a Checksum error is detected in audio data packets with audio group DID set in DATAIDB[1:0], the ADPCSB_ERR bit 4 of Host Interface register 015h will be set HIGH. When any of the above errors are detected, the ERROR external pin will also be set HIGH.
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Register Settings
NAME DBNB_ERR DESCRIPTION Ch5-8 Audio data packet DBN error detection (1:Detection) Ch5-8 Audio data packet bit8 error detection (1:Detection) Ch5-8 Audio data packet CS error detection (1:Detection) Ch1-4 Audio data packet DBN error detection (1:Detection) Ch1-4 Audio data packet bit8 error detection (1:Detection) Ch1-4 Audio data packet CS error detection (1:Detection) ADDRESS 015 BIT 7 SETTING DEFAULT 0
ADPB8B_ERR
6
-
0
GS1503
ADPCSB_ERR
4
-
0
DBNA_ERR
3
-
0
ADPB8A_ERR
2
-
0
ADPCSA_ERR
0
-
0
2.6.7 Audio Data Packet DID Setting
The audio group DID for audio output channels 1 to 4 (AOUT1/2 and AOUT3/4) is set in DATAIDA[1:0] bits 1-0 of Host Interface register 014h. The audio group DID for audio output channels 5 to 8 (AOUT5/6 and AOUT7/8) is set in DATAIDB[1:0] bits 3-2 of Host Interface register 014h. Table 12 shows the 2-bit Host Interface setting for the corresponding audio group DID. When CASCADE is set LOW (external pin or register), the GS1503 will default to audio groups 1 and 2, where AOUT1/ 2 and AOUT3/4 will be demultiplexed from audio data packets with group 1 DID, and AOUT5/6 and AOUT7/8 will be demultiplexed from audio data packets with group 2 DID. Register Settings (CASCADE set LOW)
NAME DATAIDA[1-0] DATAIDB[1-0] DESCRIPTION Ch1-4 Audio data packet DID setting Ch5-8 Audio data packet DID setting
Table 12: Audio Group DID Host Interface Settings
AUDIO GROUP 1 2 3 4 10-BIT DATA 2E7h 1E6h 1E5h 2E4h HOST INTERFACE REGISTER SETTING (2-BIT) 11b 10b 01b 00b
ADDRESS 014
BIT 1-0 3-2
SETTING See Table 12
DEFAULT 11b 10b
When CASCADE is set HIGH (external pin or register), the GS1503 will default to audio groups 3 and 4, where AOUT1/2 and AOUT3/4 will be demultiplexed from audio data packets with group 3 DID, and AOUT5/6 and AOUT7/8 will be demultiplexed from audio data packets with group 4 DID. Register Settings (CASCADE set HIGH)
NAME DATAIDA[1-0] DATAIDB[1-0] DESCRIPTION Ch1-4 Audio data packet DID setting Ch5-8 Audio data packet DID setting ADDRESS 014 BIT 1-0 3-2 SETTING See Table 12 DEFAULT 01b 00b
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2.7 DEMULTIPLEX CASCADE MODE
Two GS1503 devices can be cascaded in parallel to allow up to 16 channels of audio to be demultiplexed (only one device requires CASCADE to be set HIGH). Figure 40 shows the cascade architecture for a 16-channel system. To configure the GS1503 for cascade mode, the CASCADE
external pin or CASCADE bit 7 of Host Interface register 014h is set HIGH. When set HIGH, the GS1503 will default to audio groups 3 and 4. When set LOW, the GS1503 will default to audio groups 1 and 2.
GS1503
GS1503 Y/C b /Cr [19:0] VIN[19:0] VOUT[19:0] Y/C b /Cr [19:0]
AOUT1/2 AOUT3/4
Audio Channels 1 & 2 Audio Channels 3 & 4
Audio Group 1
AOUT5/6 AOUT7/8
Audio Channels 5 & 6 Audio Channels 7 & 8
Audio Group 2
CASCADE
GS1503 VIN[19:0] VOUT[19:0] Y/C b /Cr [19:0]
AOUT1/2 AOUT3/4
Audio Channels 9 & 10 Audio Channels 11 & 12
Audio Group 3
AOUT5/6 AOUT7/8 +3.3V CASCADE
Audio Channels 13 & 14 Audio Channels 15 & 16
Audio Group 4
Fig. 40 Demultiplexing 16 Channels of Audio using Cascade Architecture
Register Settings
NAME CASCADE DESCRIPTION Cascade enable (1: Enabled) ADDRESS 014 BIT 7 SETTING 1 DEFAULT 0
2.8 AUDIO CONTROL PACKETS 2.8.1 Audio Control Packet Detection
2.8.2 Audio Control Packet DID Setting
The audio control packet detect registers will be set HIGH when a corresponding audio group DID has been detected in the Luma channel of the input video stream. Host Interface register 020h, bits 7-4, report the individual audio groups detected.
To demultiplex audio control packets for audio channels 1 to 4 (AOUT1/2 and AOUT3/4), the CTRONA bit 2 of Host Interface register 02Fh is set HIGH. To demultiplex audio control packets for audio channels 5 to 8 (AOUT5/6 and AOUT7/8), the CTRONB bit 2 of Host Interface register 020h is set HIGH.
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Register Settings
NAME ACPG4_DET ACPG3_DET ACPG2_DET ACPG1_DET DESCRIPTION Audio group 4 control packet detection (1: Detection) Audio group 3 control packet detection (1: Detection) Audio group 2 control packet detection (1: Detection) Audio group 1 control packet detection (1: Detection) ADDRESS 020 BIT 7 6 5 4 SETTING DEFAULT 0 0 0
GS1503
0
The audio control packet group DID for audio output channels 1 to 4 is set in CTRIDA[1:0] bits 1-0 of Host Interface register 02Fh. The audio control packet group DID for audio output channels 5 to 8 is set in CTRIDB[1:0] bits 3-2 of Host Interface register 020h. Table 13 shows the 2-bit Host Interface setting for the corresponding audio control packet group DID. When CASCADE is set LOW (external pin or register), the GS1503 will default to audio groups 1 and 2, where audio control packet data for channels 1 to 4 will be demultiplexed from packets with group 1 DID, and audio control packet data for channels 5 to 8 will be demultiplexed from packets with group 2 DID. Control packet data is accessible via the corresponding registers in the Host Interface. Register Settings
NAME CTRONA DESCRIPTION
Table 13: Audio Control Packet Group DID Host Interface Settings
AUDIO GROUP 1 2 3 4 10-BIT DATA 1E3h 2E2h 2E1h 1E0h HOST INTERFACE REGISTER SETTING (2-BIT) 11b 10b 01b 00b
ADDRESS 02F
BIT 2
SETTING 1
DEFAULT 1
Ch1-4 Audio control packet demultiplex enable (1: Enabled)
CTRIDA[1:0]
Ch1-4 Audio control packet DID set
1-0
See Table 13
11b
AF_NOA[8:0]
Ch1-4 Audio frame number
030 031
0 7-0 3-1 0 -
0
RATEA[2:0] ASXA
Ch1-4 Sampling frequency data Ch1-4 Synchronization (0: Synchronous; 1: Non-synchronous)
032
0 0
DEL1-2A[25:0]
Ch1/2 Delay data
033 034 035 036
1-0 7-0 7-0 7-0 1-0 7-0 7-0 7-0 1-0 7-0 7-0
-
0
DEL3-4A[25:0]
Ch3/4 Delay data
037 038 039 03A
-
0
RSRVA[17:0]
Ch1-4 Reserved words
03B 03C 03D
-
0
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Register Settings
NAME CTRONB DESCRIPTION Ch5-8 Audio control packet demultiplex enable (1: Enabled) CTRIDB[1:0] Ch5-8 Audio control packet DID set 1-0 See Table 13 10b ADDRESS 020 BIT 2 SETTING 1 DEFAULT 1
GS1503
AF_NOB[8:0]
Ch5-8 Audio frame number
021 022
0 7-0 3-1 0
-
0
RATEB[2:0] ASXB
Ch5-8 Sampling frequency data Ch5-8 Synchronization (0: Synchronous; 1: Non-synchronous)
023
-
0 0
DEL1-2B[25:0]
Ch5/6 Delay data
024 025 026 027
1-0 7-0 7-0 7-0 1-0 7-0 7-0 7-0 1-0 7-0 7-0
-
0
DEL3-4B[25:0]
Ch7/8 Delay data
028 029 02A 02B
-
0
RSRVB[17:0]
Ch5-8 Reserved words
02C 02D 02E
-
0
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2.9 ARBITRARY DATA PACKETS
The GS1503 can demultiplex arbitrary data packets according to SMPTE 291M. Typically, arbitrary data packets consist of linear time code (LTC), vertical interval time code (VITC) or other user data, which is multiplexed once per video field. The GS1503 has two modes in which arbitrary
MSB
data can be demultiplexed from the Luma channel of the video data stream. A maximum of 255 user data words can be demultiplexed. Figure 41 shows the structure of the arbitrary data packet.
GS1503
Not b8 Parity bit
UDW252[1FC]
UDW253[1FD]
UDW251[1FB]
UDW254[1FE]
UDW254
UDW0[100]
UDW1[101]
UDW2[102]
UDW3[103]
ADF
SDID
DID
LSB
DC
User Data Words Contents available in Host Interface registers
Fig. 41 Arbitrary Data Packet Structure 2.9.1 Arbitrary Data Demultiplexing in External Pin Mode
This is the default mode for demultiplexing arbitrary data packets. The GS1503 will set the PKTEN external pin HIGH before arbitrary data will be output. Two VCLK cycles after PKTEN goes HIGH, arbitrary data is output on the PKT[7:0] bus. See Figure 42 for timing.
The following arbitrary data is output on the PKT[7:0] bus: Data ID (DID), Secondary Data ID (SDID), Data Count (DC) and User Data Words (UDW: up to a maximum of 255 words).
GS1503 Y/C b / Cr [19:0]
VIN[19:0]
PKTEN PKT[7:0]
Arbitrary Data Output Enable Arbitrary Data
2 CLKs VCLK
2 CLKs
PKTEN
PKT[7:0]
Arbitrary Data
UDW251
ADF
ADF
ADF
DID
DC
Packet
Fig. 42 Arbitrary Data Packet Output Timing Diagram
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CS
Arbitrary
UDW250
UDW252
UDW253
UDW1
UDW0
UDW2
UDW3
SDID
CS
2.9.2 Arbitrary Data Demultiplexing in Host Interface Mode
To select this mode, set ARBITMODE bit 0 in Host Interface register 050h HIGH. In this mode, the DID, SDID, DC and User Data Words must be programmed in the corresponding Host Interface registers. Set the video line number for field 1 and field 2 from which the arbitrary data packets are to be demultiplexed using the ARBITLINEA[11:0] and ARBITLINEB[11:0] Host Interface Register Settings
NAME ARBITON DESCRIPTION
registers respectively. The arbitrary data packet is demultiplexed when the ARBITON bit 1 in Host Interface register 050h is set HIGH. ARBITON should be set LOW when reading the arbitrary data packet User Data Words from the ARBITUDW Host Interface registers.
GS1503
ADDRESS 050
BIT 1
SETTING 1
DEFAULT 0
Arbitrary packet demultiplex enable (1: Enabled) Valid only when ARBITMODE is HIGH
ARBITMODE
Arbitrary packet mode selection (0: External pin mode; 1: Host mode)
0
1
0
ARBITDID[7-0] ARBITSDID[7-0] ARBITDC[7-0] ARBITLINEA[11:0]
Arbitrary packet DID setting Arbitrary packet SDID setting Arbitrary packet DC setting Field 1 multiplexing line
051 052 053 054 055
7-0 7-0 7-0 3-0 7-0 3-0 7-0 7-0
-
0 0 0 0
ARBITLINEB[11:0]
Field 2 multiplexing line
056 057
-
0
ARBITUDW
Arbitrary packet UDW
100-1FE
-
0
2.10 ANCILLARY DATA DELETION
The GS1503 can be configured to delete the embedded ancillary data packets, after demultiplexing. There are two modes for ancillary data deletion.
2.10.1 Entire Ancillary Data Deletion
When the ANCI external pin or ANCI bit 1 of Host Interface register 040h is set HIGH, all ancillary data packets in both the Luma and Chroma channel of the input video stream are deleted. The data is replaced with blanking values 040h in the Luma channel and 200h in the Chroma channel. The DEL_SEL bit 0 of Host Interface register 040h must be set LOW.
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2.10.2 Audio Group Designation Ancillary Data Deletion
When the ANCI bit 1 of Host Interface register 040h is set HIGH, and DEL_SEL bit 0 of Host Interface register 040h is HIGH, only audio data and control packets which are designated in Host Interface registers 041h will be deleted. To delete the arbitrary data packets, the corresponding DID must be set in the NDID[7:0] Host Interface register 042h.
GS1503
Register Settings
NAME ANCI DEL_SEL DESCRIPTION Ancillary data packet delete (1: Deletion enabled) Ancillary data packet delete mode select (0: Entire data delete; 1: Group designated data delete) ADPG4_DEL ADPG3_DEL ADPG2_DEL ADPG1_DEL ACPG4_DEL ACPG3_DEL ACPG2_DEL ACPG1_DEL NDID[7:0] Audio group 4 data packet delete (1: Delete) Audio group 3 data packet delete (1: Delete) Audio group 2 data packet delete (1: Delete) Audio group 1 data packet delete (1: Delete) Audio group 4 control packet delete (1: Delete) Audio group 3 control packet delete (1: Delete) Audio group 2 control packet delete (1: Delete) Audio group 1 control packet delete (1: Delete) Arbitrary packet DID delete setting 042 041 7 6 5 4 3 2 1 0 7-0 0 0 0 0 0 0 0 0 0 ADDRESS 040 BIT 1 0 SETTING 1 1 DEFAULT 0 0
2.11 DEMULTIPLEX MODE WITH WORD CLOCK INPUT
Some commercially available HD audio embedding modules do not encode the audio word clock phase information correctly in the CLK words of the audio data packet. If this clock information is not correctly encoded, the GS1503 will not output the audio data correctly. Also, the GS1503 will be unable to reproduce the 48kHz audio word clock (fs) at the WCOUTA and WCOUTB pins in serial audio output modes. If the GS1503 is to be used in conjunction with a HD audio module, which encodes audio clock phase information incorrectly, the DEC_MODE external pin or DECMODE bit 2 of Host Interface register 01Eh must be set HIGH. When Register Settings
NAME DECMODE DESCRIPTION
HIGH, an audio word clock synchronous to the original word clock used for embedding must be input at the WCINA and WCINB pins. Figure 43 shows a system example. When the embedded clock phase data for audio channel 1 to 4 is detected as being in error, the MUXERRA bit 0 of Host Interface register 01Eh will be set HIGH. Similarly, when the embedded clock phase data for audio channel 5 to 8 is detected as being in error, the MUXERRB bit 1 of Host Interface register 01Eh will be set HIGH
ADDRESS 01E
BIT 2
SETTING 1
DEFAULT 0
Demultiplex Mode with word clock input enable (1: Enabled)
MUXERRB
Ch5-8 embedded clock phase information error detect (1: Detected) Ch1-4 embedded clock phase information error detect (1: Detected)
1
-
0
MUXERRA
0
-
0
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HD Audio Embedding Module Y/C b / C r [19:0] VIN[19:0] GS1503 VOUT[19:0] Y/C b /Cr [19:0]
Audio Channels 1 & 2 Audio Channels 3 & 4 48kHz (fs)
AIN1/2 AIN3/4 WCINA WCINA
AOUT1/2 AOUT3/4
Audio Channels 1 & 2
GS1503
Audio Channels 3 & 4
Audio Channels 5 & 6 Audio Channels 7 & 8 48kHz (fs)
AIN5/6 AIN7/8 WCINA +3.3V DEC_MODE MUX/DEMUX WCINA AOUT5/6 AOUT7/8 Audio Channels 5 & 6 Audio Channels 7 & 8
Fig. 43 Demultiplex Mode with 48kHz Word Clock Input System Example
Figure 44 shows the timing relationship between the audio word clock inputs and word clock outputs when the GS1503 is configured to serial audio output mode.
1 CLK ACLKA/B
WCINA/B
WCOUTA/B
Fig. 44 WCINA/B Input to WCOUTA/B Output Timing Diagram
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Table 14: Demultiplex Mode Host Interface Registers
CONTROL ITEM Video NAME VM_SEL DESCRIPTION Video input format (external pin/internal register) configuration select. When set LOW, the video input format is configured via the VM[3:0] pins. When set HIGH, the video input format is configured via the "VM[3:0]" bits. Video signal detection flag. Set HIGH when 3 consecutive TRS are detected in the input video signal. Video input signal CRC error detection. Set HIGH when a CRC error is detected in the input video signal. This register is refreshed on every video frame. Video CRC insertion. When set HIGH, the Luma and Chroma line CRC words are re-calculated and inserted into the output video signal. Video input format selection. See Table 10. Valid when "VM_SEL" is HIGH. External EXTH/EXTF input select. When set LOW, the EXTH and EXTF pins are configured as outputs. When set HIGH, the GS1503 will insert TRS and Line Numbers based on signals input at the EXTH and EXTF pins. Scramble processing bypass select. When set HIGH, the internal scrambler and NRZ(I) encoder is bypassed. NOTE: The status of the SCRBYPASS external pin is not updated in this register. The value programmed in this register is logical OR'd with the SCRBYPASS external pin setting. 8BIT_SEL DSCBYPASS 8-bit input selection. When set HIGH, the GS1503 will accept an 8-bit input video signal. Descramble process bypass select. When set HIGH, the internal SMPTE 292M descrambler is bypassed. NOTE: The status of the DSCBYPASS external pin is not updated in this register. The value programmed in this register is logical OR'd with the DSCBYPASS external pin setting. CRC_CNT[11:0] CRC error accumulation. Reports the accumulated number of CRC errors in one video frame. Not used. Vertical blanking enable. When set HIGH, the output video vertical blanking will be set to 040h for the Luma channel and 200h for the Chroma channel. Horizontal blanking enable. When set HIGH, the output video horizontal blanking, including TRS, line numbers and line CRC words, will be set to 040h for the Luma channel and 200h for the Chroma channel. NOTE: If blanking of line numbers and TRS words is required, LN_INS and TRS_INS must be set LOW. 006 007 008 3-0 7-0 7-4 3 R/W R/W 0 0 R 0 1 0 R/W R/W 0 0 001 ADDRESS 000 BIT 7 R/W R/W DEFAULT 0
GS1503
VIDEO_DET
6
R
0
CRC_ERR
5
R
0
CRC_INS
4
R/W
1
VM[3:0] EXT_SEL
3-0 3
R/W R/W
0 0
SCRBYPASS
2
R/W
0
RSV VBLK_INS
HBLK_INS
2
R/W
0
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Table 14: Demultiplex Mode Host Interface Registers (Continued)
CONTROL ITEM NAME LN_INS DESCRIPTION Line insertion enable. When set HIGH, the GS1503 will insert line numbers into the video data stream. When set LOW, existing line numbers will remain in the output video stream. TRS insertion enable. When set HIGH, the GS1503 will insert TRS codes into the video data stream. When set LOW, existing TRS codes will remain in the output video stream. Audio input format (external pin/register) configuration select. When set LOW, the audio input format is configured via the AM[1:0] pins. When set HIGH, the audio input format is configured via the "AM[1:0]" bits. Not used. Audio input format select. See Table 11. Valid when "AM_SEL" is HIGH. Not used. Demultiplex Mode select. When set HIGH, the GS1503 requires a 48kHz word clock input at WCINA and WCINB. This word clock must be synchronous to the word clock used to embed the audio data. The embedded clock information in the audio data packet will be ignored. See Section 2-11. NOTE: The status of the DEC_MODE external pin is not updated in this register. The value programmed in this register is logical OR'd with the DEC_MODE external pin setting. MUXERRB Ch5-8 audio sample clock error. When set HIGH, the GS1503 is unable to recover the audio clock phase data in the embedded audio data packet for audio channels 5 to 8. See Section 2-11. Ch1-4 audio sample clock error. When set HIGH, the GS1503 is unable to recover the audio clock phase data in the embedded audio data packet for audio channels 1 to 4. See Section 2-11. Audio Channel Status. When "CS_MODE" is set HIGH, the 23 8-bit bytes of the Audio Channel Status Block, as defined in AES3-1992, are available in these registers. Valid in both AES/EBU and serial audio modes. When "CS_MODE" is set LOW, the Audio Channel Status information in the AES/EBU audio outputs will be replaced with data programmed in these registers. Valid only in AES/EBU audio mode. RSV Not used 06F 7-6 0 058 : 06E 1 R 0 01E 010 ADDRESS BIT 1 R/W R/W DEFAULT 1
GS1503
TRS_INS
0
R/W
1
Audio
AM_SEL
7
R/W
0
RSV AM[1:0] RSV DECMODE
6-2 1-0 7-3 2
R/W R/W
0 0 0 0
MUXERRA
0
R
0
Audio Channel Status Block
AUDIO_CS[7:0] : AUDIO_CS [183:176]
7-0 : 7-0
R
0
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Table 14: Demultiplex Mode Host Interface Registers (Continued)
CONTROL ITEM NAME CS_WEND DESCRIPTION Audio Channel Status write flag. When set HIGH, indicates that the audio channel status information has been written into the Host Interface registers 058h to 06Eh and can be read by the user. Valid only when "CS_MODE" is set HIGH. Audio Channel Status request. When set HIGH, the GS1503 will read and store the Audio Channel Status information from the audio channel set in Host Interface register "CH_SEL[2:0]". Valid only when "CS_MODE" is set HIGH. Audio Channel Status mode. When set HIGH, the user can access the embedded Audio Channel Status information from the Host Interface registers 058h to 06Eh. Valid in both AES/EBU and serial audio modes. When set LOW, the Audio Channel Status information for all audio outputs will be replaced with data programmed in Host Interface registers 058h - 06Eh. Valid only in AES/EBU audio mode. CH_SEL[2:0] Audio Channel Status select. Designates the embedded audio channel from which the Audio Channel Status information will be demultiplexed. The setting 000b represent audio channel 1, through to 111b for channel 8. Valid only when "CS_MODE" is set HIGH. 2-0 R/W 000b ADDRESS BIT 5 R/W R DEFAULT 0
GS1503
CS_RQST
4
R/W
0
CS_MODE
3
R/W
0
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Table 14: Demultiplex Mode Host Interface Registers (Continued)
CONTROL ITEM Audio Data Packet NAME ADPG4_DET DESCRIPTION Audio group 4 data packet detect. When set HIGH, audio data packets with group 4 DID have been detected in the incoming Chroma video data stream. NOTE: Once this bit has been set, it will remain set until a device reset is performed. ADPG3_DET Audio group 3 data packet detect. When set HIGH, audio data packets with group 3 DID have been detected in the incoming Chroma video data stream. NOTE: Once this bit has been set, it will remain set until a device reset is performed. ADPG2_DET Audio group 2 data packet detect. When set HIGH, audio data packets with group 2 DID have been detected in the incoming Chroma video data stream. NOTE: Once this bit has been set, it will remain set until a device reset is performed. ADPG1_DET Audio group 1 data packet detect. When set HIGH, audio data packets with group 1 DID have been detected in the incoming Chroma video data stream. NOTE: Once this bit has been set, it will remain set until a device reset is performed. RSV ECCB_ON Not used. Ch5-8 error correction enable. When set HIGH, the GS1503 will perform error correction on audio data packets for channels 5 to 8, based on the six ECC words. Ch1-4 error correction enable. When set HIGH, the GS1503 will perform error correction on audio data packets for channels 1 to 4, based on the six ECC words. 3-2 1 R/W 0 1 4 R 0 5 R 0 6 R 0 ADDRESS 013 BIT 7 R/W R DEFAULT 0
GS1503
ECCA_ON
0
R/W
1
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Table 14: Demultiplex Mode Host Interface Registers (Continued)
CONTROL ITEM NAME CASCADE DESCRIPTION Cascade select. When set HIGH, the GS1503 will default to audio groups 3 and 4. When set LOW, the GS1503 will default to audio groups 1 and 2. NOTE: The status of the CASCADE external pin is not updated in this register. The value programmed in this register is logical OR'd with the CASCADE external pin setting. RSV AMUTEB Not used. Ch5-8 audio mute enable. When set HIGH, the multiplexed audio packets for audio channels 5 to 8 are forced to zero. NOTE: The status of the MUTE external pin is not updated in this register. The value programmed in this register is logical OR'd with the MUTE external pin setting. AMUTEA Ch1-4 audio mute enable. When set HIGH, the multiplexed audio packets for audio channels 1 to 4 are forced to zero. NOTE: The status of the MUTE external pin is not updated in this register. The value programmed in this register is logical OR'd with the MUTE external pin setting. DATAIDB[1:0] Ch5-8 audio group DID setting. Designates the audio group DID for audio channels 5 to 8. See Table 12. When CASCADE (external pin or register) is set LOW, the default setting is audio group 2. When CASCADE is set HIGH, the default setting is audio group 4. Ch1-4 audio group DID setting. Designates the audio group DID for audio channels 1 to 4. See Table 12. When CASCADE (external pin or register) is set LOW, the default setting is audio group 1. When CASCADE is set HIGH, the default setting is audio group 3. 3-2 R/W 10b 4 R/W 0 6 5 R/W 0 0 ADDRESS 014 BIT 7 R/W R/W DEFAULT 0
GS1503
DATAIDA[1:0]
1-0
R/W
11b
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Table 14: Demultiplex Mode Host Interface Registers (Continued)
CONTROL ITEM NAME DBNB_ERR DESCRIPTION Ch5-8 audio data packet DBN error. When set HIGH, a Data Block Number error has been detected in the audio data packet for audio channels 5 to 8. Ch5-8 audio data packet 'bit 8' error. When set HIGH, a 'bit 8' error has been detected in the audio data packet for audio channels 5 to 8. Ch5-8 audio data packet error. When set HIGH, an error has been detected in the audio data packet for audio channels 5 to 8, based on the six ECC words. Ch5-8 audio data packet CS error. When set HIGH, a Checksum error has been detected with the audio data packet for audio channels 5 to 8. Ch1-4 audio data packet DBN error. When set HIGH, a Data Block Number error has been detected in the audio data packet for audio channels 1 to 4. Ch1-4 audio data packet 'bit 8' error. When set HIGH, a 'bit 8' error has been detected in the audio data packet for audio channels 1 to 4. Ch1-4 audio data packet error. When set HIGH, an error has been detected in the audio data packet for audio channels 1 to 4, based on the six ECC words. Ch1-4 audio data packet CS error. When set HIGH, a Checksum error has been detected with the audio data packet for audio channels 1 to 4. Ch5-8 ECC correctable packets. Designates the number of audio data packets for channels 5 to 8 that have been corrected in one video frame using the BCH forward error correction system. Ch5-8 ECC un-correctable packets. Designates the number of audio data packets for channels 5 to 8 that could not be corrected in one video frame using the BCH forward error correction system. Ch1-4 ECC correctable packets. Designates the number of audio data packets for channels 1 to 4 that have been corrected in one video frame using the BCH forward error correction system. Ch1-4 ECC un-correctable packets. Designates the number of audio data packets for channels 1 to 4 that could not be corrected in one video frame using the BCH forward error correction system. 016 017 ADDRESS 015 BIT 7 R/W R DEFAULT 0
GS1503
ADPB8B_ERR
6
R
0
ECCB_ERR
5
R
0
ADPCSB_ERR
4
R
0
DBNA_ERR
3
R
0
ADPB8A_ERR
2
R
0
ECCA_ERR
1
R
0
ADPCSA_ERR
0
R
0
CORRECTB [11:0]
3-0 7-0
R
0
NO_CORRECTB [11:0]
018 019
3-0 7-0
R
0
CORRECTA [11:0]
01A 01B
3-0 7-0
R
0
NO_CORRECTA [11:0]
01C 01D
3-0 7-0
R
0
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Table 14: Demultiplex Mode Host Interface Registers (Continued)
CONTROL ITEM Audio Control Packet NAME ACPG4_DET DESCRIPTION Audio group 4 control packet detect. When set HIGH, audio control packets with group 4 DID have been detected in the incoming Luma video data stream. Audio group 3 control packet detect. When set HIGH, audio control packets with group 3 DID have been detected in the incoming Luma video data stream. Audio group 2 control packet detect. When set HIGH, audio control packets with group 2 DID have been detected in the incoming Luma video data stream. Audio group 1 control packet detect. When set HIGH, audio control packets with group 1 DID have been detected in the incoming Luma video data stream. Not used. Ch5-8 audio control packet demultiplex enable. When set HIGH, the audio control packets in the Luma channel of the video data stream for audio channels 5 to 8 will be demultiplexed. Ch5-8 audio control packet DID setting. Designates the audio control packet DID for audio channels 5 to 8. See Table 13. The default setting is audio group 2. Ch5-8 audio frame number. Designates the audio frame number for audio channels 5 to 8. Ch5-8 sampling frequency. Designates the audio sampling frequency for audio channels 5 to 8, taken from the RATE word of the audio control packet as defined in SMPTE 299M. Ch5-8 synchronization. When set HIGH, the "asx" bit of the audio control packet RATE word designates audio channels 5 to 8 as asynchronous, as per SMPTE 299M. When set LOW, the "asx" bit of the audio control packet RATE word designates synchronous audio. Ch5/6 delay data. Designates the accumulated audio processing delay relative to video for audio channels 5 and 6. 024 025 026 027 DEL3-4B[25:0] Ch7/8 delay data. Designates the accumulated audio processing delay relative to video for audio channels 7 and 8. 028 029 02A 02B RSRVB[17:0] Ch5-8 reserve words. Designates the value set in the RSRV words of the audio control packet for audio channels 5 to 8, as per SMPTE 299M. 02C 02D 02E 021 022 023 ADDRESS 020 BIT 7 R/W R DEFAULT 0
GS1503
ACPG3_DET
6
R
0
ACPG2_DET
5
R
0
ACPG1_DET
4
R
0
RSV CTRONB
3 2
R/W
0 1
CTRIDB[1:0]
1-0
R/W
10b
AF_NOB[8:0]
0 7-0 3-1
R/W
0
RATEB[2:0]
R/W
0
ASXB
0
R/W
0
DEL1-2B[25:0]
1-0 7-0 7-0 7-0 1-0 7-0 7-0 7-0 1-0 7-0 7-0
R/W
0
R/W
0
R/W
0
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Table 14: Demultiplex Mode Host Interface Registers (Continued)
CONTROL ITEM NAME RSV CTRONA Not used. Ch1-4 audio control packet demultiplex enable. When set HIGH, the audio control packets in the Luma channel of the video data stream for audio channels 1 to 4 will be demultiplexed. Ch1-4 audio control packet DID setting. Designates the audio control packet DID for audio channels 1 to 4. See Table 13. The default setting is audio group 1. Ch1-4 audio frame number. Designates the audio frame number for audio channels 1 to 4. Ch1-4 sampling frequency. Designates the audio sampling frequency for audio channels 1 to 4, taken from the RATE word of the audio control packet as defined in SMPTE 299M. Ch1-4 synchronization. When set HIGH, the "asx" bit of the audio control packet RATE word designates audio channels 1 to 4 as asynchronous, as per SMPTE 299M. When set LOW, the "asx" bit of the audio control packet RATE word designates synchronous audio. Ch1/2 delay data. Designates the accumulated audio processing delay relative to video for audio channels 1 and 2. 033 034 035 036 DEL3-4A[25:0] Ch3/4 delay data. Designates the accumulated audio processing delay relative to video for audio channels 3 and 4. 037 038 039 03A RSRVA[17:0] Ch1-4 reserve words. Designates the value set in the RSRV words of the audio control packet for audio channels 1 to 4, as per SMPTE 299M. Not used. Ancillary data delete. When set HIGH, all ancillary data packets ("DEL_SEL" is LOW) or ancillary data packets with DIDs designated in Host Interface registers 041h and 042h ("DEL_SEL" is HIGH) are removed from the video signal. The ancillary data packets are replaced with blanking codes. The data contained in the packets are output at the corresponding pins. When set LOW, all ancillary data packets remain in the video signal. NOTE: The status of the ANCI external pin is not updated in this register. The value programmed in this register is logical OR'd with the ANCI external pin setting DEL_SEL Ancillary data delete mode select. When set HIGH, individual audio groups can be deleted from the video signal by programming Host Interface register 041h. When set LOW, all ancillary data packets are deleted from the video signal. 0 R/W 0 03B 03C 03D 040 030 031 032 DESCRIPTION ADDRESS 02F BIT 7-3 2 R/W R/W DEFAULT 0 1
GS1503
CTRIDA[1:0]
1-0
R/W
11b
AF_NOA[8:0]
0 7-0 3-1
R/W
0
RATEA[2:0]
R/W
0
ASXA
0
R/W
0
DEL1-2A[25:0]
1-0 7-0 7-0 7-0 1-0 7-0 7-0 7-0 1-0 7-0 7-0 7-2 1
R/W
0
R/W
0
R/W
0
Packet Delete
RSV ANCI
R/W
0 0
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Table 14: Demultiplex Mode Host Interface Registers (Continued)
CONTROL ITEM NAME ADPG4_DEL DESCRIPTION Audio group 4 data packet delete. When set HIGH, all audio data packets with group 4 DID will be deleted from the Chroma video data stream. Valid only when "DEL_SEL" is HIGH. Audio group 3 data packet delete. When set HIGH, all audio data packets with group 3 DID will be deleted from the Chroma video data stream. Valid only when "DEL_SEL" is HIGH. Audio group 2 data packet delete. When set HIGH, all audio data packets with group 2 DID will be deleted from the Chroma video data stream. Valid only when "DEL_SEL" is HIGH. Audio group 1 data packet delete. When set HIGH, all audio data packets with group 1 DID will be deleted from the Chroma video data stream. Valid only when "DEL_SEL" is HIGH. Audio group 4 control packet delete. When set HIGH, all audio control packets with group 4 DID will be deleted from the Luma video data stream. Valid only when "DEL_SEL" is set HIGH. To be fixed. Audio group 3 control packet delete. When set HIGH, all audio control packets with group 3 DID will be deleted from the Luma video data stream. Valid only when "DEL_SEL" is HIGH. To be fixed. Audio group 2 control packet delete. When set HIGH, all audio control packets with group 2 DID will be deleted from the Luma video data stream. Valid only when "DEL_SEL" is HIGH. To be fixed. Audio group 1 control packet delete. When set HIGH, all audio control packets with group 1 DID will be deleted from the Luma video data stream. Valid only when "DEL_SEL" is HIGH. To be fixed. Arbitrary data packet delete. Designates the DID for the arbitrary data packets to be deleted from the Luma video data stream. Valid only when "DEL_SEL" is HIGH. 042 ADDRESS 041 BIT 7 R/W R/W DEFAULT 0
GS1503
ADPG3_DEL
6
R/W
0
ADPG2_DEL
5
R/W
0
ADPG1_DEL
4
R/W
0
ACPG4_DEL
3
R/W
0
ACPG3_DEL
2
R/W
0
ACPG2_DEL
1
R/W
0
ACPG1_DEL
0
R/W
0
NDID[7:0]
7-0
R/W
0
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Table 14: Demultiplex Mode Host Interface Registers (Continued)
CONTROL ITEM Arbitrary Data Packet NAME ARBITON DESCRIPTION Arbitrary data packet demultiplex. Valid only when "ARBITMODE" is HIGH. When set HIGH, arbitrary data packets will be demultiplexed from the Luma video data stream. Must be set LOW again to access valid data in the "ARBITUDW" registers. Arbitrary packet mode select. When set HIGH, arbitrary data packets are demultiplexed and the User Data Words are stored in Host Interface registers 100h to 1FEh. No data will be output on the PKT[7:0] external pins and PTKTEN will be LOW. When set LOW, arbitrary data packets are demultiplexed and output at the PKT[7:0] external pins. Arbitrary packet Data ID setting. Designates the 8 LSBs of the DID word of the arbitrary data packet to be demultiplexed. The 2 MSBs are internally generated. "ARBITDID[7]" is the MSB and "ARBITDID[0]" is the LSB. Valid only when "ARBITMODE" is HIGH. Arbitrary packet Secondary Data ID setting. Designates the 8 LSBs of the secondary DID word of the arbitrary data packet to be demultiplexed. The 2 MSBs are internally generated. "ARBITSDID[7]" is the MSB and "ARBITSDID[0]" is the LSB. Valid only when "ARBITMODE" is HIGH. Arbitrary packet DC setting. Designates the 8 LSBs of the Data Count word of the arbitrary data packet to be demultiplexed. The 2 MSBs are internally generated. "ARBITDC[7]" is the MSB and "ARBITDC[0]" is the LSB. Valid only when "ARBITMODE" is HIGH. Field 2 arbitrary packet demultiplex line number setting. Designates the field 2 video line from which the arbitrary data packets will be demultiplexed. Valid only when "ARBITMODE" is HIGH. Field 1 arbitrary packet demultiplex line number setting. Designates the field 1 video line from which the arbitrary data packets will be demultiplexed. Valid only when "ARBITMODE" is HIGH. Arbitrary packet User Data Word. Designates the 8 LSBs for up to 255 arbitrary packet User Data Words. Arbitrary data can be read from these registers once "ARBITON" has been set HIGH to LOW. Valid only when "ARBITMODE" is HIGH. 051 ADDRESS 050 BIT 1 R/W R/W DEFAULT 0
GS1503
ARBITMODE
0
R/W
0
ARBITDID[7:0]
7-0
R/W
0
ARBITSDID[7:0]
052
7-0
R/W
0
ARBITDC[7:0]
053
7-0
R/W
0
ARBITLINEB [11:0]
054 055
3-0 7-0
R/W
0
ARBITLINEA [11:0]
056 057
3-0 7-0
R/W
0
ARBITUDW0 : ARBITUDW254
100 : 1FE
7-0 : 7-0
R/W
0
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VCC VCC U1 R1 55R T2 4 3 5 C1 220n R2 191R
2
3
8
U2
/ R DE VCC E A R1 B7 GND
J1 BNC_BCJ_RPC_01
AESIN1/2
8 1 R5 100R PE-65812 2 R3 55R 8 2 T1
G D / RE DE N
3 1 7B 4D
1
5 6
PE-65812 4 6A
VCC
8
J2 BNC_BCJ_RPC_01 1
AESOUT1/2
R4 75R 5 VCC VCC SN75176B(R) 5 2 C2 100n 3 SN75176B(D)
3. REFERENCE DESIGN
3.1 CIRCUIT SCHEMATICS
2
3
8
U4
/ RE DE VCC
8
U3 R6 55R T4 4 1 R10 100R PE-65812 2 R8 55R 8 5 BNC_BCJ_RPC_01 1 3 J4 6 7 C3 220n R7 191R
AESIN3/4
3
R
J3 BNC_BCJ_RPC_01 1 5
A
PE-65812 4 1
B GND G D / RE DE N
6A 7B 1 4D
VCC
AESOUT3/4
8 2 R9 75R T3 5 VCC VCC U12 R70 55R T6 4 1 R72 55R PE-65812 SN75176B(D) 8 R73 100R 2 5 6 7 C99 220n R71 191R 2 3
/ RE DE VCC
SN75176B(R) 5 2 C4 100n 3
SN75176B(D)
AESIN5/6
R
3 5 1
B GD N
PE-65812
VCC A
8
U13
8
J10 BNC_BCJ_RPC_01 1 4 4D 1 T5
G D / RE DE N
6A 7B
J11 BNC_BCJ_RPC_01 1
3
AESOUT5/6
8 2 R74 75R SN75176B(R) 5 2 C100 100n VCC VCC 3 5
2
3
8
U15
/ R DE VCC E
8
U14 R75 55R
A
2
R78 75R T7
GND / R E DE
GND
R77 55R 5 SN75176B(D)
R79 100R PE-65812
SN75176B(R) 5 2 C102 100n GS1503 3
GS1545
GS1522
2
AIN7/8
AIN5/6
AIN3/4
AIN1/2
AOUT1/2
AOUT5/6
SDI IN
SDI VIN[19..0] VCLK_1503 VCLK_1522 VCLK_CPU LT_SDO VCLK_CPU VCLK_1522 RESETn RESETn VCLK_1503 VCLK_1503 VIN[19..0] VIN[19..0]
AOUT7/8
3
J5 BNC_BCJ_RPC_01 1 VOUT[19..0]
AOUT3/4
2
2
2
2
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AESIN7/8
R
3 8 1 7B 1 4D
J12 BNC_BCJ_RPC_01 1 5 PE-65812 4 6A
VCC B
T8 6 7 4 1 5 8
C101 220n
R76 191R
J13 BNC_BCJ_RPC_01 1 3
AESOUT7/8
J6 SDO0 VOUT[19..0] CPUADR[8..0] VCLK_1522 VOUT[19..0] VCLK_1522 BNC_BCJ_RPC_01 1 3
SDI OUT 1
CPUADR[8..0] CPUDAT[7..0]
CPUDAT[7..0]
A_GND CPUCSn CPUREn CPUWEn CPUCSn CPUREn CPUWEn SDO1 BNC_BCJ_RPC_01 1 J8 3
SDI LOOP THRU
3
J7 BNC_BCJ_RPC_01 1
SDI OUT 2
AUDIO ENDEC SERIALIZER
RECEIVER
VCC CPUADR[8..0] JP1
MISC
RESETn CPUDAT[7..0]
RESETn
CPU INTERFACE
CPUADR8 CPUADR7 CPUADR6 CPUADR5 CPUADR4 CPUADR3 CPUADR2 CPUADR1 CPUADR0 CPUDAT0 CPUDAT1 CPUDAT2 CPUDAT3 CPUDAT4 CPUDAT5 CPUDAT6 CPUDAT7 CPUCSn CPUREn CPUWEn RESETn VCLK_CPU
47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 CONN 24X2
48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2
POWER & RESET
GS1503
15879 - 4
VCC_VCO1
GS1545 VCO POWER PLANE
100n C51 GND_VCO1 R49 VCC C52 10u 3 2 GND VCTR VCC GND_VCO1 1 C53 100n R50 C54 10n 0R C55 1u VCC_VCO1 10u 0R
C50
4 GND GND
U7 GO1515 8 O/P GND NC GND_VCO1
GND_VCO1 5 6 GND_VCO1 VCC_VCO1 C56 10n C58 GND_VCO1 10n GND_VCO1 D6 GND_VCO1 11 R53 2 VCC_VCO1 22k GND_VCO1 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 VCC_VCO1 nc nc nc nc PLL_LOCK nc PLCAP nc nc PLCAP nc VCO nc VCO nc nc IJI LFS nc nc nc LFS DM DM nc nc DFT_VEE LFA_VEE LBCONT LFA LFA_VCC nc nc nc nc nc nc nc VIN[19..0] 3 10n 1u 1u C59 C60 C61 Q2 2N3904/TO R52 0 VCC_VCO1 C57 10n R51 150 2 7
VCC_VCO1
VIN[19..0]
R54 5k VIN19 VIN18 VIN17 VIN16 VIN15 VIN14
U8 GS1545
VIN13 VIN12 VIN11 VIN10
VCC
VCC_VCO1
GND_VCO1 C65 A_VCC L3 R55 75 C66 C67 R56 75 A_GND R57 37R5 47p 47p A_GND 10n 1.5p
A_GND
R58 A_VCC C71 1u A_GND A_VCC A_GND C72 10n C73 10n VCC A_VCC
0R IC5 VCC VCC R60 22 EMF3 BLM11A601S +3.3V C74 10u A_GND BLM11A601S EMF4 +3.3V C77 10u C79 100n VCC VCC C78 100n C82 C83 100n R61 75 5 U9 SDI 2 R64 50 R65 50 SDI VEE GND VCC 1 SDO SDO RSET GS1508 3 6 8 7 4 R66 53R6 C86 10n R62 37R4 L4 C84 R63 12n 0.5p 75 C85 4u7 LT_SDO 10n C80 100n C81 100n C75 100n C76 100n VCLKIN 13 24 11 23 1 2 10 14 22 6 7 18 19 FBIN CLK G AVCC AGND VCC VCC VCC VCC GND GND GND GND CDC2510C VCLK_1522 VCLK_1503 VCLK_CPU
VCC
C68 10u
C69 100n
R59
0R
C70 10n
ANALOG POWER PLANE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
nc nc nc nc MCLADJ nc CLI nc nc nc nc CD EQO_VEE nc nc EQO_VCC SDO SDO SDO_VEE SDO_EN SDO_VCC nc nc nc nc nc nc nc nc SP_VCC SP_VCC SP_VEE SP_VEE PCLK_OUT PCLK_VCC PCLK_VEE nc nc
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VIN9 VIN8 VIN7 VIN6 VIN5 VIN4 VIN3 VIN2 VIN1 VIN0
C62 10n
C63 10n
C64 10n
SDI
103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 nc nc BYPASS DDI_VTT nc DDI DDI PD_VCC A/D PDSUB_VEE PD_VEE nc nc nc EQI_VCC nc nc EQI_VEE nc SDI nc SDI nc EQI_VEE nc nc DATA_OUT19 DATA_OUT18 DATA_OUT17 DATA_OUT16 DATA_OUT15 DATA_OUT14 nc nc DATA_OUT13 DATA_OUT12 DATA_OUT11 DATA_OUT10 nc nc DATA_OUT9 DATA_OUT8 DATA_OUT7 DATA_OUT6 DATA_OUT5 DATA_OUT4 DATA_OUT3 DATA_OUT2 DATA_OUT1 DATA_OUT0 nc nc
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39
FBOUT 1Y0 1Y1 1Y2 1Y3 1Y4 1Y5 1Y6 1Y7 1Y8 1Y9
12 3 4 5 8 9 15 16 17 20 21
GS1503
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+3.3V
1
C103 2 10u 2 VOUT[19..0] IC1 10u
C104
VIN[19..0]
1
D1 PG1101W 2 D2 PG1101W 2 D3 BR1101W 2 D4 BR1101W 2 1 R14 1k 1 R13 1k 1 R12 1k 1 R11 1k
VIN19 VIN18 VIN17 VIN16 VIN15 VIN14 VIN13 VIN12 VIN11 VIN10 VIN9 VIN8 VIN7 VIN6 VIN5 VIN4 VIN3 VIN2 VIN1 VIN0 110 111 112 114 115 116 118 119 120 122 123 124 126 127 128 130 131 132 134 135 VIN19 VIN18 VIN17 VIN16 VIN15 VIN14 VIN13 VIN12 VIN11 VIN10 VIN9 VIN8 VIN7 VIN6 VIN5 VIN4 VIN3 VIN2 VIN1 VIN0 EXTH EXTF PKTEN PKTENO 24 VIDEO_DET OPERATE ERROR CRC_ERR VIDEO_DET OPERATE ERROR CRC_ERR VOUT19 VOUT18 VOUT17 VOUT16 VOUT15 VOUT14 VOUT13 VOUT12 VOUT11 VOUT10 VOUT9 VOUT8 VOUT7 VOUT6 VOUT5 VOUT4 VOUT3 VOUT2 VOUT1 VOUT0 43 44 25 45 22 21 23 71 70 69 67 66 65 63 62 61 59 58 57 55 54 53 51 50 49 47 46 VOUT19 VOUT18 VOUT17 VOUT16 VOUT15 VOUT14 VOUT13 VOUT12 VOUT11 VOUT10 VOUT9 VOUT8 VOUT7 VOUT6 VOUT5 VOUT4 VOUT3 VOUT2 VOUT1 VOUT0
C5 R15 VCC C6 680p 2 8 R16 10k X1 VCC IC6A + 1 NC GND OUT TLC2272 1 8 4 14 3 R18 2 180R R19 10k 7 DSCBYPASS SCRBYPASS DEC_MODE 8 38 85 C7 100n G 100k 10n WCOUTA WCOUTB 74 75
26 28 29 30 32 33 34 35 PKT7 PKT6 PKT5 PKT4 PKT3 PKT2 PKT1 PKT0 VCC EMF1 DSS310-55D-223 S 3 1 I O C8 100n WCINA WCINB 7 6
+3.3V IC2A 4 S 2 3 74FCT7 4 5 D C R Q 12 11 +3.3V Q VCC GND 1
+3.3V 10 IC2B S 9 D C R 6 14 7 Q Q 8 74FCT7 4 13 R17 33R ACLKA
AIN1/2 AIN3/4 AIN5/6 AIN7/8 PLLCNTA PLLCNTB 10 9 PLLCNTA PLLCNTB
AIN1/2 AIN3/4 AIN5/6 AIN7/8 5 4 3 2 AIN1/2 AIN3/4 AIN5/6 AIN7/8 AOUT1/2 AOUT3/4 AOUT5/6 AOUT7/8 AOUT1/2 AOUT3/4 AOUT5/6 AOUT7/8 76 77 78 79
AOUT1/2 AOUT3/4 AOUT5/6 AOUT7/8
RESETn
VCLK_150 3
VCXO-920B1-24.576MHz +3.3V
R20 * PLACE CLOSE TO GS1503 INPUT C9 PIN * +3.3V ANCI MUTE VCC C11 680p 8 R22 10k 3 + 4 R24 2 +3.3V R25 10k 180R 1 TLC2272 IC7A 1 NC GND X2 14 10n 100k C10 R21
RESETn VCLK_150 3 ACLKA ACLKB MUXn/DEMUX VM3 VM2 VM1 VM0 CPU_SEL 143 87 17 19 15 139 140 141 142 136 137 138 13 11 12 RESETn VCLK ACLKA ACLKB MUXn/DEMUX VM3 VM2 VM1 VM0 CPU_SEL AM1 AM0 ANCI CASCADE MUTE
G
4
2
C12 100n VCC
C13 100n 2 OUT 8 3 74FCT7 4 VCXO-920B1-24.576MHz 7 +3.3V D C
S
Q
5
12 11 +3.3V R Q VCC GND 1
S
10
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
R
CPUDAT7 CPUDAT6 CPUDAT5 CPUDAT4 CPUDAT3 CPUDAT2 CPUDAT1 CPUDAT0 103 102 101 100 99 98 96 95 CPUDAT7 CPUDAT6 CPUDAT5 CPUDAT4 CPUDAT3 CPUDAT2 CPUDAT1 CPUDAT0 CPUCSn CPUREn CPUWEn RSV RSV RSV RSV GS1503 105 106 107 39 40 41 42 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 144 129 121 113 108 88 86 80 72 64 56 48 36 20 18 16 CPUCSn CPUREn CPUWEn
+3.3V
CPUCSn CPUREn CPUWEn
R27 R29 10K 10K R26 R28 10K 10K +3.3V
+3.3V S1 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C94 C95 C96 C97 C98 MUTE ANCI MUXn/DEMUX CPU_SEL
100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n
100n
1 2 3 4 5 6 7 8 9 10 KHS10
20 19 18 17 16 15 14 13 12 11
VM3 VM2 VM1 VM0
+3.3V R31 R33 10K 10K R30 R32 10K 10K
GS1503
13
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CPUADR8 CPUADR7 CPUADR6 CPUADR5 CPUADR4 CPUADR3 CPUADR2 CPUADR1 CPUADR0 81 82 83 89 94 93 92 91 90 CPUADR8 CPUADR7 CPUADR6 CPUADR5 CPUADR4 CPUADR3 CPUADR2 CPUADR1 CPUADR0 133 125 117 109 104 97 84 73 68 60 52 37 31 27 14 1
+3.3V
CPUADR[8..0]
VCC EMF2 DSS310-55D-223 S 3 1 O I
+3.3V IC4A
+3.3V IC4B 9 D C 6 14 7 Q Q 8 74FCT7 4 R23 33R ACLKB
CPUDAT[7..0]
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R34
C26
VCC_VCO2 GND_VCO2 C27 100n C28 GND_VCO2 10u 0R VCC_VCO2 3 2 1 VCC GND VCTR C29 1u GND_VCO2 GND 8 C30 0R 10n R36 C31 100n C32 10u VCC R35
49R9
1u
4 GND O/P GND NC
U5 GO1515
GND_VCO2 5 6 7
GND_VCO2
GND_VCO2 VCC_VCO2 GND_VCO2 VCC_VCO2 C33 GND_VCO2 C35 VCC R37 VCC 0 GND_VCO2 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 C38 10n GND_VCO2 C39 10n C36 10n C37 10n 10n VCC 1u 1u VCC_VCO2 C34
GS1522 VCO POWER PLANE
VCC
VOUT[19..0]
VOUT[19..0]
nc nc nc nc nc nc SYN_DETECT_DISABLE VEE3 VCC3 nc LFA_VCC LBCONT LFA LFA_VEE DFT_VEE PLCAP DM PLCAP LFS nc LFS nc nc PD_VCC IJI PDSUB_VEE PD_VEE VCO VCO nc nc nc nc nc nc nc nc nc
VOUT19 VOUT18 VOUT17 VOUT16 VOUT15
R38 75
R39 37R4
C40 L1
0.5p 12n R41 75R C41 4u7 SDO0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
VEE3 PCLK_IN nc nc nc nc nc nc nc BUF_VEE nc nc XDIV20 nc PLL_LOCK BYPASS RESET VEE2 nc nc VCC2 VCC2 VCC2 VCC2 VCC2 VEE2 VEE2 VEE2 VEE2 VEE2 SDO1_EN nc nc nc nc nc nc nc
2
11
GS1503
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3
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VCC R40 53.6 VOUT14 VOUT13 VOUT12 VOUT11 VOUT10 VOUT9
U6 GS1522
C42 L2 R42
0.5p 12n 75R C43 4u7 SDO1
VOUT8 VOUT7
VCC R45 53.6 C44 10n VCC C45 10n R43 37R4 R44 75
VOUT6 VOUT5 VOUT4 VOUT3 VOUT2 VOUT1 VOUT0
103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 DATA_IN19 DATA_IN18 DATA_IN17 DATA_IN16 DATA_IN15 nc nc DATA_IN14 DATA_IN13 DATA_IN12 DATA_IN11 DATA_IN10 DATA_IN9 nc nc DATA_IN8 DATA_IN7 nc nc DATA_IN6 DATA_IN5 DATA_IN4 DATA_IN3 DATA_IN2 DATA_IN1 DATA_IN0 OSC_VEE A0 nc nc nc VEE2 RSET0 VCC2 nc SDO0 SDO0_NC SDO0 nc nc nc SDO1 SDO_NC SDO1 nc VCC2 RSET1 nc nc nc nc nc
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39
VCC C46 10n
VCLK_1522 VCC C48
C47 10n 1u
VCC
R46 * PLACE CLOSE TO GS1522 INPUT C49 PIN *
R47 150R
D5
Q1 2N3904/TO 2 R48 22k
LOCK_DETECT
GS1503
J9 1 2 3 4 1 2 3 4 2 VCC R67 470R C87 100uF/6.3V C88 100n
LP 5.00/4/90 D7 5V PWR 1 U10 LM1085_M VOUT 2 ADJ 1 3 VIN
EMF5 BLM31P330S G VCC C89 100uF/6.3V C90 100n
+3.3V R68 300R 2 C91 100uF/6.3V C92 100n
D8 3.3V PWR 1 VCC VCC R69 4K7 1 4 U11 MR PFI 2 VCC
GND
S2 STM1- 01
VCC
RESET RESET NC PFO MAX707
8 7 6 5
RESETn
VCC C93 100n
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3
3.2 BOARD LAYOUTS
GS1503
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GS1503
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GS1503
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3.3
ITEM 1 2
BILL OF MATERIALS
QUANTITY 4 41 REFERENCE C1,C3,C99,C101 C2,C4,C7,C8, C12,C13,C14, C15,C16,C17, C18,C19,C20, C21,C22,C23, C24,C25,C27, C31,C50,C53, C69,C75,C76, C78,C79,C80, C81,C83,C88, C90,C92,C93,C94,C95,C96, C97,C98,C100, C102 L3,C5,C10,C30,C35,C36, C37,C38,C39,C44,C45,C46, C47,C54,C56,C57,C58,C59, C62,C63,C64,C70,C72,C73, C82,C86 C6,C11 C9,R20,R46,C49 C26,C29,C33,C34,C48,C55, C60,C61,C71 C28,C32,C51,C52,C68,C74, C77,C103,C104 C40,C42,C84 C41,C43,C85 C65 C66,C67 C87,C89,C91 D1,D2,D3,D4,D5,D6,D7,D8 EMF1,EMF2 EMF3,EMF4 EMF5 IC1 IC2,IC4 IC5 IC6,IC7 JP1 J1,J2,J3,J4,J5,J6,J7,J8, J10,J11,J12,J13 J9 L1,L2,L4 Q2,Q1 R1,R3,R6,R8,R70,R72,R75, R77 R2,R7,R71,R76 R4,R9,R41,R42,R74,R78 R5,R10,R73,R79 R11,R12,R13,R14 R21,R15 PART 220n 100n
GS1503
3
26
10n
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
2 4 9 9 3 3 1 2 3 4 2 2 1 1 2 1 2 1 12 1 3 2 8 4 6 4 4 2
680p * 1u 10u 0.5p 4u7 1.5p 47p 100uF/6.3V PG1101W DSS310-55D-223S BLM11A601S BLM31P330SG GS1503 74FCT74 CDC2510C TLC2272 CONN 24X2 BNC_BCJ_RPC_01 LP 5.00/4/90 12n 2N3904/TO 55R 191R 75R 100R 1k 100k
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3.3
ITEM 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
BILL OF MATERIALS (Continued)
QUANTITY 12 2 2 3 8 6 3 3 1 2 1 1 1 1 1 1 1 1 1 8 4 4 2 1 1 1 1 1 2 REFERENCE R16,R19,R22,R25,R26,R27, R28,R29,R30,R31,R32,R33 R17,R23 R24,R18 R34,R64,R65 R35,R36,R37,R49,R50,R52,R58, R59 R38,R44,R55,R56,R61,R63 R39,R43,R62 R40,R45,R66 R47 R53,R48 R51 R54 R57 R60 R67 R68 R69 S1 S2 T1,T2,T3,T4,T5,T6,T7,T8 U1,U3,U12,U14 U2,U4,U13,U15 U7,U5 U6 U8 U9 U10 U11 X2,X1 PART 10K 33R 180R
GS1503
49R9 0R 75R 37R4 53R6 150R 22k 150R 5k 37R5 22R 470R 300R 4K7 KHS10 STM1-01 PE-65812 SN75176B(D) SN75176B(R) GO1515 GS1522 GS1545 GS1508 LM1085_M MAX707 VCXO-920B1-24.576MHz
NOTE: This design is recommended for reference only. The AES/EBU inputs do not utilize equalization; therefore cable length performance may be limited. For improved AES/EBU input and output performance, it is recommended that examples in the AES-3id-2001 standard Annex B are consulted. This standard includes alternative schematics for both input and output networks for 75 coaxial cable transmission. For the transmission of AES/EBU over balanced 110 twisted pair cable, using XLR type connectors, please consult the AES3-1992 standard
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4. REFERENCES & BIBLIOGRAPHY SMPTE 260M-1999 1125/60 High-Definition Production System - Digital Representation and Bit-Parallel Interface SMPTE 274M-1998 1920 x 1080 Scanning and Analog and Parallel Digital Interfaces for Multiple Picture Rates SMPTE 291M-1998 Ancillary Data Packet and Space Formatting SMPTE 292M-1998 Bit-Serial Digital Interface for High-Definition Television Systems SMPTE 295M-1997 1920 x 1080 50 Hz - Scanning and Interfaces SMPTE 296M- 2001 1280 x 720 Scanning, Analog and Digital Representation and Analog Interface SMPTE 299M-1997 24-Bit Digital Audio Format for HDTV Bit-Serial Interface SMPTE RP211-2000 Implementation of 24P, 25P and 30P Segmented Frames for 1920 x 1080 Production Format AES3-1992 (ANSI S4.40-1992) AES Recommended practice for digital audio engineering - Serial transmission format for two-channel linearly represented digital audio data AES-3id-2001 AES information document for digital audio engineering - Transmission of AES3 formatted data by unbalanced coaxial cable EBU Tech. 3250-E Specification of the Digital Audio Interface (The AES/EBU Interface) (Second Edition 1992) Society of Motion Picture and Television Engineers: http://www.smpte.org Audio Engineering Society: http://www.aes.org European Broadcast Union: http://www.ebu.ch
GS1503
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PACKAGING INFORMATION
22 0.4
20 0.1 108 73
GS1503
109
72 View on A-A
22 0.4
12 NOM
20 0.1 A 12 NOM 0.50 0.2 37 1.0 REF +0.05 0.125 -0.025 0 MIN 10 MAX
INDEX 144
1
36 1.40 0.1
1.70 MAX 144 pin LQFP (FZ) Dimensions in millimetres 0.2 +0.1 -0.05 0.1
0.5
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REVISION HISTORY
VERSION 2 ECR 132133 DATE September 2003 CHANGES AND/OR MODIFICATIONS Modified Host Interface Register 014 description (multiplex mode only). Added revision history. Fixed typing errors (page 24 and 33, Table 8, and Table 14). Added note to Section 1.11. Added note to Section 1.6.2.2 clarifying that serial audio data is clocked by the GS1503 using a 3.072MHz clock. Corrected Packaging Information.
3
133576
June 2004
GS1503
4
136656
May 2005
DOCUMENT IDENTIFICATION
DATA SHEET The product is in production. Gennum reserves the right to make changes at any time to improve reliability, function or design, in order to provide the best product possible.
CAUTION
ELECTROSTATIC SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION
GENNUM CORPORATION
Mailing Address: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Shipping Address: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 GENNUM JAPAN CORPORATION Shinjuku Green Tower Building 27F, 6-14-1, Nishi Shinjuku, Shinjuku-ku, Tokyo, 160-0023 Japan Tel. +81 (03) 3349-5501, Fax. +81 (03) 3349-5505 GENNUM UK lIMITED 25 Long Garden Walk, Farnham, Surrey, England GU9 7HX Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523 Gennum Corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. The sale of the circuit or device described herein does not imply any patent license, and Gennum makes no representation that the circuit or device is free from patent infringement. GENNUM and the G logo are registered trademarks of Gennum Corporation. (c) Copyright 2001 Gennum Corporation. All rights reserved. Printed in Canada. www.gennum.com
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